AT32F421 Series Reference Manual
2022.11.11 Page 256 Rev 2.02
14.6 Advanced-control timers (TMR1)
14.6.1 TMR1 introduction
The advanced-control timer TMR1 consists of a 16-bit counter supporting up, down or up/down counting
modes, four capture/compare registers, and four independent channels to achieve embedded dead-time,
input capture and programmable PWM output.
14.6.2 TMR1 main features
Source of counter clock: internal clock, external clock an internal trigger input
16-bit up, down, up/down, repetition and encoder mode counter
Four independent channels for input capture, output compare, PWM generation, one-pulse mode
output and embedded dead-time
Three independent channels for complementary output
TMR brake function
Synchronization control between master and slave timers
Interrupt/DMA is generated at overflow event, trigger event, brake signal input and channel event
Support TMR burst DMA transfer
Figure 14-91 Block diagram of advanced-control timer
14.6.3 TMR1 functional overview
14.6.3.1 Count clock
The counter of TMR1 can be clocked by the internal clock (CK_INT), external clock (external clock mode
A and B) and internal trigger input (ISx).
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