ARTERY AT32F421C8T7 - DMA Interrupt Status Register (DMA_STS)

AT32F421 Series Reference Manual
2022.11.11 Page 103 Rev 2.02
9.4.1 DMA interrupt status register (DMA_STS)
Access: 0 wait state, accessible by bytes, half-words or words.
Bit
Register
Reset value
Type
Description
Bit 31: 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
DTERRF5
0x0
ro
Channel 5 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 18
HDTF5
0x0
ro
Channel 5 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 17
FDTF5
0x0
ro
Channel 5 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 16
GF5
0x0
ro
Channel 5 global event flag
0: No transfer error, half transfer or transfer complete
event occurred.
1: Transfer error, half transfer or transfer complete event
Bit 15
DTERRF4
0x0
ro
Channel 4 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 14
HDTF4
0x0
ro
Channel 4 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 13
FDTF4
0x0
ro
Channel 4 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 12
GF4
0x0
ro
Channel 4 global event flag
0: No transfer error, half transfer or transfer complete
event occurred.
1: Transfer error, half transfer or transfer complete event
Bit 11
DTERRF3
0x0
ro
Channel 3 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 10
HDTF3
0x0
ro
Channel 3 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 9
FDTF3
0x0
ro
Channel 3 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 8
GF3
0x0
ro
Channel 3 global event flag
0: No transfer error, half transfer or transfer complete
event occurred.
1: Transfer error, half transfer or transfer complete event
Bit 7
DTERRF2
0x0
ro
Channel 2 data transfer error event flag
0: No transfer error occurred.
1: Transfer error occurred.
Bit 6
HDTF2
0x0
ro
Channel 2 half transfer event flag
0: No half-transfer event occurred.
1: Half-transfer event occurred.
Bit 5
FDTF2
0x0
ro
Channel 2 transfer complete event flag
0: No transfer complete event occurred.
1: Transfer complete event occurred.
Bit 4
GF2
0x0
ro
Channel 2 global event flag
0: No transfer error, half transfer or transfer complete
event occurred.
1: Transfer error, half transfer or transfer complete event