ARTERY AT32F421C8T7 - APB1 Peripheral Clock Enable Register (CRM_APB1 EN)

AT32F421 Series Reference Manual
2022.11.11 Page 55 Rev 2.02
4.3.8 APB1 peripheral clock enable register (CRM_APB1EN)
Access: by words, half-words and bytes.
No-wait states in most cases. However, when accessing to peripherals on APB1, wait-states are inserted
until the end of peripheral access on the APB1 bus.
Bit
Name
Reset value
Type
Description
Bit 31: 29
Reserved
0x0
resd
Kept at its default value.
Bit 28
PWCEN
0x0
rw
PWC clock enable
0: Disabled
1: Enabled
Bit 27: 23
Reserved
0x00
resd
Kept at its default value.
Bit 22
I2C2EN
0x0
rw
I2C2 clock enable
0: Disabled
1: Enabled
Bit 21
I2C1EN
0x0
rw
I2C1 clock enable
0: Disabled
1: Enabled
Bit 20: 18
Reserved
0x0
resd
Kept at its default value.
Bit 17
USART2EN
0x0
rw
USART2 clock enable
0: Disabled
1: Enabled
Bit 16: 15
Reserved
0x0
resd
Kept at its default value.
Bit 14
SPI2EN
0x0
rw
SPI2 clock enable
0: Disabled
1: Enabled
Bit 13: 12
Reserved
0x0
resd
Kept at its default value.
Bit 11
WWDTEN
0
rw
WWDT clock enable
0: Disabled
1: Enabled
Bit 10: 9
Reserved
0x0
resd
Kept at its default value.
Bit 8
TMR14EN
0x0
rw
TMR14 clock enable
0: Disabled
1: Enabled
Bit 7: 5
Reserved
0x0
resd
Kept at its default value.
Bit 4
TMR6EN
0x0
rw
TMR6 clock enable
0: Disabled
1: Enabled
Bit 3: 2
Reserved
0x0
resd
Kept at its default value.
Bit 1
TMR3EN
0x0
rw
TMR3 clock enable
0: Disabled
1: Enabled
Bit 0
Reserved
0x0
resd
Kept at its default value.