ARTERY AT32F421C8T7 - Battery Powered Domain Control Register (CRM_BPDC); Control;Status Register (CRM_CTRLSTS)

AT32F421 Series Reference Manual
2022.11.11 Page 56 Rev 2.02
4.3.9 Battery powered domain control register (CRM_BPDC)
Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case
of consecutive accesses to this register.
Note: LEXTEN, LEXTBYPS, ERTCSEL, and ERTCEN bits of the battery powered domain control
register (CRM_BPDC) are in the battery powered domain. As a result, these bits are write protected after
reset, and can only be modified by setting the BPWEN bit in the power control register (PWR_CTRL).
These bits could be reset only by battery powered domain reset. Any internal or external reset does not
affect these bits.
Bit
Name
Reset value
Type
Description
Bit 31: 17
Reserved
0x0000
resd
Kept at its default value.
Bit 16
BPDRST
0x0
rw
Battery powered domain software reset
0: Do not reset battery powered domain software
1: Reset battery powered domain software
Bit 15
ERTCEN
0x0
rw
ERTC clock enable
Set and cleared by software.
0: Disabled
1: Enabled
Bit 14: 10
Reserved
0x00
resd
Kept at its default value.
Bit 9: 8
ERTCSEL
0x0
rw
ERTC clock selection
Once the ERTC clock source is selected, it cannot be
changed until the BPDRST bit is reset.
00: No clock
01: LEXT
10: LICK
11: HEXT/128
Bit 7: 3
Reserved
0x00
resd
Kept at its default value.
Bit 2
LEXTBYPS
0x0
rw
Low speed external crystal bypass
0: Disabled
1: Enabled
Bit 1
LEXTSTBL
0x0
ro
Low speed external oscillator stable
Set by hardware after the LEXT is ready.
0: LEXT is not ready.
1: LEXT is ready.
Bit 0
LEXTEN
0x0
rw
External low-speed oscillator enable
0: Disabled
1: Enabled
4.3.10 Control/status register (CRM_CTRLSTS)
Reset flag can only be cleared by power reset or by setting the RSTFC bit, while others are cleared by
system reset.
Access: 0 to 3 wait states, accessible by words, half-words or bytes. Wait states are inserted in the case
of consecutive accesses to this register.
Bit
Name
Reset value
Type
Description
Bit 31
LPRSTF
0x0
ro
Low-power reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No low-power reset occurs
1: Low-power reset occurs
Bit 30
WWDTRSTF
0x0
ro
Window watchdog timer reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No window watchdog timer reset occurs
1: Window watchdog timer reset occurs
Bit 29
WDTRSTF
0x0
ro
Watchdog timer reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No watchdog timer reset occurs
1: Watchdog timer reset occurs.
Bit 28
SWRSTF
0x0
ro
Software reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No software reset occurs
1: Software reset occurs.