ARTERY AT32F421C8T7 - Additional Register (CRM_MISC2)

AT32F421 Series Reference Manual
2022.11.11 Page 59 Rev 2.02
4.3.14 Additional register (CRM_MISC2)
Bit
Name
Reset value
Type
Description
Bit 31: 10
Reserved
0x000000
resd
Kept at its default value.
Bit 9
HICK_TO_SCLK
0x0
rw
HICK as system clock frequency select
When the HICK is selected as the clock source SCLKSEL,
the frequency of SCLK is:
0: Fixed 8 MHz, that is, HICK/6
1: 48 MHz or 8 MHz, depending on the HICKDIV
Bit 8: 6
Reserved
0x0
resd
Kept at its default value.
Bit 5: 4
AUTO_STEP_EN
0x0
rw
Auto step-by-step system clock switch enable
When the system clock source is switched from others to
the PLL or when the AHB prescaler is changed from large
to small (system frequency is from small to large), it is
recommended to enable the auto step-by-step system
clock switch if the operational target is larger than 108
MHz,.
Once it is enabled, the AHB bus is halted by hardware till
the completion of the switch. During this switch period, the
DMA remain working, and the interrupt events are
recorded and then handled by NVIC when the AHB bus
resumes.
00: Disabled
01: Reserved
10: Reserved
11: Enabled. When AHBDIV or SCLKSEL is modified, the
auto step-by-step
Bit 3: 0
Reserved
0xd
resd
Kept at its default value.