ARTERY AT32F421C8T7 - SPI Registers; SPI Control Register1 (SPI_CTRL1); Mode; Table 13-2 SPI Register Map and Reset Value

AT32F421 Series Reference Manual
2022.11.11 Page 166 Rev 2.02
13.4 SPI registers
These peripheral registers must be accessed by half-word (16 bits) or word (32 bits).
Table 13-2 SPI register map and reset value
Register
Offset
Reset value
SPI_CTRL1
0x00
0x0000
SPI_CTRL2
0x04
0x0000
SPI_STS
0x08
0x0002
SPI_DT
0x0C
0x0000
SPI_CPOLY
0x10
0x0007
SPI_RCRC
0x14
0x0000
SPI_TCRC
0x18
0x0000
SPI_I2SCTRL
0x1C
0x0000
SPI_I2SCLKP
0x20
0x0002
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I
2
S mode)
Bit
Register
Reset value
Type
Description
Bit 15
SLBEN
0x0
rw
Single line bidirectional half-duplex enable
0: Disabled
1: Enabled
Bit 14
SLBTD
0x0
rw
Single line bidirectional half-duplex transmission direction
This bit and the SLBEN bit together determine the data
output direction in “Single line bidirectional half-duplex”
mode.
0: Receive-only mode
1: Transmit-only mode
Bit 13
CCEN
0x0
rw
RC calculation enable
0: Disabled
1: Enabled
Bit 12
NTC
0x0
rw
Transmit CRC next
When this bit is set, it indicates that the next data
transferred is CRC value.
0: Next transmitted data is the normal value
1: Next transmitted data is CRC value
Bit 11
FBN
0x0
rw
Frame bit num
This bit is used to configure the number of data frame bit
for transmission/reception.
0: 8-bit data frame
1: 16-bit data frame
Bit 10
ORA
0x0
rw
Receive-only active
In two-wire unidirectional mode, when this bit is set, it
indicates that Receive-only is active, but the transmit is
not allowed.
0: Transmission and reception
1: Receive-only mode
Bit 9
SWCSEN
0x0
rw
Software CS enable
When this bit is set, the CS pin level is determined by the
SWCSIL bit. The status of I/O level on the CK pin is
invalid.
0: Disabled
1: Enabled
Bit 8
SWCSIL
0x0
rw
Software CS internal level
This bit is valid only when the SWCSEN is set. It
determines the level on the CS pin.
In master mode, this bit must be set.
0: Low level
1: High level