ARTERY AT32F421C8T7 - Clock Control Register (CRM_CTRL)

AT32F421 Series Reference Manual
2022.11.11 Page 49 Rev 2.02
4.3.1 Clock control register (CRM_CTRL)
No-wait states, accessible by bytes, half-words or words.
Bit
Name
Reset value
Type
Description
Bit 31: 26
Reserved
0x00
resd
Kept at its default value.
Bit 25
PLLSTBL
0x0
ro
PLL clock stable
This bit is set by hardware after PLL is ready.
0: PLL clock is not ready.
1: PLL clock is ready.
Bit 24
PLLEN
0x0
rw
PLL enable
This bit is set and cleared by software. It can also be
cleared by hardware when entering Standby or
Deepsleep mode. When the PLL clock is used as the
system clock, this bit cannot be cleared.
0: PLL is OFF
1: PLL is ON.
Bit 23: 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
CFDEN
0x0
rw
Clock failure detector enable
0: OFF
1: ON
Bit 18
HEXTBYPS
0x0
rw
High speed external crystal bypass
This bit can be written only if the HEXT is disabled.
0: OFF
1: ON
Bit 17
HEXTSTBL
0x0
ro
High speed external crystal stable
This bit is set by hardware after HEXT becomes stable.
0: HEXT is not ready.
1: HEXT is ready.
Bit 16
HEXTEN
0x0
rw
High speed external crystal enable
This bit is set and cleared by software. It can also be
cleared by hardware when entering Standby or
Deepsleep mode. When the HEXT clock is used as the
system clock, this bit cannot be cleared
0: OFF.
1: ON
Bit 15: 8
HICKCAL
0xXX
rw
High speed internal clock calibration
The default value of this field is the initial factory
calibration value.
When the HICK output frequency is 48 MHz, it needs
adjust 240 kHz (design value) based on this frequency for
each HICKCAL value change; when HICK output
frequency is 8 MHz (design value), it needs adjust 40 kHz
based on this frequency for each HICKCAL value change.
Note: This bit can be written only if the HICKCAL_KEY[7:
0] is set as 0x5A.
Bit 7: 2
HICKTRIM
0x20
rw
High speed internal clock trimming
These bits work with the HICKCAL[7: 0] to determine the
HICK oscillator frequency. The default value is 32, which
can trim the HICK to be ±1%.
Bit 1
HICKSTBL
0x1
ro
High speed internal clock stable
This bit is set by hardware after the HICK is ready.
0: Not ready
1: Ready
Bit 0
HICKEN
0x1
rw
High speed internal clock enable
This bit is set and cleared by software. It can also be set
by hardware when exiting Standby or Deepsleep mode.
When a HEXT clock failure occurs. This bit can also be
set. When the HICK is used as the system clock, this bit
cannot be cleared.
0: Disabled
1: Enabled