ARTERY AT32F421C8T7 - APB2 Peripheral Reset Register (CRM_APB2 RST)

AT32F421 Series Reference Manual
2022.11.11 Page 52 Rev 2.02
1: Enabled
Bit 7
CFDF
0x0
ro
Clock Failure Detection flag
This bit is set by hardware when the HEXT
clock failure occurs.
0: No clock failure
1: Clock failure
Bit 6: 5
Reserved
0x0
resd
Keep at its default value.
Bit 4
PLLSTBLF
0x0
ro
PLL stable flag
Set by hardware.
0: PLL is not ready.
1: PLL is ready.
Bit 3
HEXTSTBLF
0x0
ro
HEXT stable flag
Set by hardware.
0: HEXT is not ready.
1: HEXT is ready.
Bit 2
HICKSTBLF
0x0
ro
HICK stable flag
Set by hardware.
0: HICK is not ready.
1: HICK is ready.
Bit 1
LEXTSTBLF
0x0
ro
LEXT stable flag
Set by hardware.
0: LEXT is not ready.
1: LEXT is ready.
Bit 0
LICKSTBLF
0x0
ro
LICK stable interrupt flag
Set by hardware.
0: LICK is not ready.
1: LICK is ready.
4.3.4 APB2 peripheral reset register (CRM_APB2RST)
Access: 0 wait state, accessible by words, half-words and bytes.
Bit
Name
Reset value
Type
Description
Bit 31: 19
Reserved
0x0000
resd
Kept at its default value.
Bit 18
TMR17ST
0x0
resd
TMR17 reset
0: Does not reset TMR17
1: Reset TMR17
Bit 17
TMR16ST
0x0
rw
TMR16 set
0: Does not reset TMR16
1: Reset TMR16
Bit 16
TMR15ST
0x0
rw
TMR15 reset
0: Does not reset TMR15
1: Reset TMR15
Bit 15
Reserved
0x0
resd
Kept at its default value.
Bit 14
USART1RST
0x0
rw
USART1 reset
0: Does not reset USART1
1: Reset USART1
Bit 13
Reserved
0x0
resd
Kept at its default value.
Bit 12
SPI1RST
0x0
rw
SPI1 reset
0: Does not reset SPI1
1: Reset SPI1
Bit 11
TMR1RST
0x0
rw
TMR1 reset
0: Does not reset TMR1
1: Reset TMR1
Bit 10
Reserved
0x0
resd
Kept at its default value.
Bit 9
ADCRST
0x0
rw
ADC reset
0: Does not reset ADC
1: Reset ADC
Bit 8: 2
Reserved
0x00
resd
Kept at its default value.
Bit 1
EXINTRST
0x0
rw
EXINT reset
0: Does not reset EXINT
1: Reset EXINT
Note: This bit is always 0 when reading by software.
Bit 0
SCFGCMPRST
0x0
rw
SCFG and CMP reset
0: Does not reset SCFG and CMP