ARTERY AT32F421C8T7 - Guard Time and Divider Register (USART_GDIV)

AT32F421 Series Reference Manual
2022.11.11 Page 148 Rev 2.02
1: Smartcard mode is enabled.
Bit 4
SCNACKEN
0x0
rw
Smartcard NACK enable
This bit is used to send NACK when parity error occurs.
0: NACK is disabled when parity error occurs.
1: NACK is enabled when parity error occurs.
Bit 3
SLBEN
0x0
rw
Single-wire bidirectional half-duplex enable
0: Single-wire bidirectional half-duplex is disabled.
1: Single-wire bidirectional half-duplex is enabled.
Bit 2
IRDALP
0x0
rw
IrDA low-power mode
This bit is used to configure IrDA low-power mode.
0: IrDA low-power mode is disabled.
1: IrDA low-power mode is enabled.
Bit 1
IRDAEN
0x0
rw
IrDA enable
0: IrDA is disabled.
1: IrDA is enabled.
Bit 0
ERRIEN
0x0
rw
Error interrupt enable
An interrupt is generated when a framing error, overflow
error or noise error occurs.
0: Error interrupt is disabled.
1: Error interrupt is enabled.
12.12.7 Guard time and divider register (USART_GDIV)
Bit
Register
Reset value
Type
Description
Bit 31: 16
Reserved
0x0000
resd
Forced 0 by hardware.
Bit 15: 8
SCGT
0x00
rw
Smartcard guard time value
This field specifies the guard time value. The transmission
complete flag is set after this guard time in smartcard
mode.
Bit 7: 0
ISDIV
0x00
rw
IrDA/smartcard division
In IrDA mode:
8 bit [7: 0] is valid. It is valid in common mode and must
be set to 00000001. In low-power mode, it divides the
peripheral clock to serve as the period base of the pulse
width;
00000000: Reserved–Do not write.
00000001: Divided by 1
00000010: Divided by 2
……
Smartcard mode:
The lower 5 bit [4: 0] is valid. This division is used to divide
the peripheral clock to provide clock for the Smartcard.
Configured as follows:
00000: Reserved–Do not write.
00001: Divided by 2
00010: Divided by 4
00011: Divided by 6
……