ARTERY AT32F421C8T7 - DEBUG Control Register (DEBUG_CTRL)

AT32F421 Series Reference Manual
2022.11.11 Page 334 Rev 2.02
22.4.2 DEBUG control register (DEBUG_CTRL)
This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the
debugger under reset.
Bit
Register
Reset value
Type
Description
Bit 31: 28
Reserved
0x0000
resd
Kept at its default value.
Bit 27
TMR14_PAUSE
0x0
rw
TMR14 pause control bit
0: Work normally
1: Timer is disabled
Bit 26: 25
Reserved
0x0
resd
Kept at its default value.
Bit 24
TMR17_PAUSE
0x0
rw
TMR17 pause control bit
0: Work normally
1: Timer is disabled
Bit 23
TMR16_PAUSE
0x0
rw
TMR16 pause control bit
0: Work normally
1: Timer is disabled
Bit 22
TMR15_PAUSE
0x0
rw
TMR15 pause control bit
0: Work normally
1: Timer is disabled
Bit 21
ERTC_512_PAUSE
0x0
rw
ERTC512Hz pause control bit
0: Work normally when ERTC512Hz
1: Receive register stops receiving data when
ERTC512HZ.
Bit 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
TMR6_PAUSE
0x0
rw
TMR6 pause control bit
0: Work normally
1: Timer is disabled
Bit 18: 17
Reserved
0x0
resd
Kept at its default value.
Bit 16
I2C2_SMBUS_TIMEOUT
0x0
rw
I2C2 pause control bit
0: Work normally
1: I2C2 SMBUS timeout control is disabled
Bit 15
I2C1_SMBUS_TIMEOUT
0x0
rw
I2C1 pause control bit
0: Work normally
1: I2C1 SMBUS timeout control is disabled
Bit 14
ERTC_PAUSE
0x0
rw
ERTC pause control bit
0: ERTC works normally
1: ERTC receive registers stops receiving data.
Bit 13
Reserved
0x0
resd
Kept at its default value.
Bit 12
TMR3_PAUSE
0x0
rw
TMR3 pause control bit
0: Work normally
1: Timer is disabled
Bit 11
Reserved
0x0
resd
Kept at its default value.
Bit 10
TMR1_PAUSE
0x0
rw
TMR1 pause control bit
0: Work normally
1: Timer is disabled
Bit 9
WWDT_PAUSE
0x0
rw
Window watchdog pause control bit
0: Window watchdog works normally
1: Window watchdog is stopped
Bit 8
WDT_PAUSE
0x0
rw
watchdog pause control bit
0: Watchdog works normally
1: Watchdog is stopped
Bit 7: 3
Reserved
0x00
resd
Kept at its default value.
Bit 2
STANDBY_DEBUG
0x0
rw
Debug Standby mode control bit
0: The whole 1.2V digital circuit is unpowered in Standby