ARTERY AT32F421C8T7 - TMR16 and TMR17 DMA Control Register (Tmrx_Dmactrl); TMR16 and TMR17 DMA Data Register (Tmrx_Dmadt)

AT32F421 Series Reference Manual
2022.11.11 Page 255 Rev 2.02
14.5.4.14 TMR16 and TMR17 DMA control register
(TMRx_DMACTRL)
Bit
Register
Reset value
Type
Description
Bit 15:13
Reserved
0x0
resd
Kept at its default value.
Bit 12:8
DTB
0x00
rw
DMA transfer bytes
This field defines the number of DMA transfers:
00000: 1 byte 00001: 2 bytes
00010: 3 bytes 00011: 4 bytes
...... ......
10000: 17 bytes 10001: 18 bytes
Bit 7:5
Reserved
0x0
resd
Kept at its default value.
Bit 4: 0
ADDR
0x00
rw
DMA transfer address offset
ADDR is defined as an offset starting from the address
of the TMRx_CTRL1 register:
00000: TMRx_CTRL1
00001: TMRx_CTRL2
00010: TMRx_STCTRL
......
14.5.4.15 TMR16 and TMR17 DMA data register (TMRx_DMADT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
DMADT
0x0000
rw
DMA data register
A write/read operation to the DMADT register accesses
any TMR register located at the following address:
TMRx peripheral address + ADDR*4 to TMRx peripheral
address + ADDR*4 + DTB*4