ARTERY AT32F421C8T7 - Clock Control Register (I2 C_ CLKCTRL); Clock Rise Time Register (I2 C_TMRISE)

AT32F421 Series Reference Manual
2022.11.11 Page 129 Rev 2.02
cleared by hardware on detection of a Stop condition.
Bit 0
TRMODE
0x0
ro
Transmission mode
0: Slave mode
1: Master mode
Set by hardware when the GENSTART is set and a Start
condition is sent. Cleared by hardware when a Stop
condition is detected.
11.5.8 Clock control register (I2C_ CLKCTRL)
Bit
Register
Reset value
Type
Description
Bit 15
SPEEDMODE
0x0
rw
Speed mode selection
0: Standard mode (up to 100 kHz)
1: Fast mode (up to 400 kHz)
In fast mode, an accurate 400kHz clock is generated
when the I
2
C clock frequency is an integer multiple of
10MHz.
Bit 14
DUTYMODE
0x0
rw
Fast mode duty cycle
0: The ratio of High to low is 1:2.
1: The ratio of low to high is 9:16.
Bit 13: 12
Reserved
0x0
resd
Kept at its default value.
Bit 11: 0
SPEED
0x000
rw
I
2
C bus speed config
In standard mode:
High level= SPEED x T
I2C_CLK
Low level= SPEED x T
I2C_CLK
In fast mode:
DUTYMODE = 0:
High level= SPEED x T
I2C_CLK
x 1
Low level= SPEED x T
I2C_CLK
x 2
DUTYMODE = 1:
High level= SPEED x T
I2C_CLK
x 9
Low level= SPEED x T
I2C_CLK
x 16
The minimum value allowed in standard mode is 4. In fast
mode, the minimum value allowed is 1.
The CLKCTRL register can be configured only when the
I2C is disabled (I2CEN=0).
Note: The I2C_CLKCTRL register can be configured only when the I2C is disabled
(I2CEN=0).
11.5.9 Clock rise time register (I2C_TMRISE)
Bit
Register
Reset value
Type
Description
Bit 15: 6
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 5: 0
RISETIME
0x02
rw
I2C bus rise time
Time= RISETIME x T
I2C_CLK
In standard mode, I2C protocol stand is 1000ns, and the
formula is:
RISETIME = F
I2C_CLK
+1
For example, when I2C clock is 48MHz, RISETIME = 48+1
In fast mode, I2C protocol stand is 300ns, and the formula
is:
RISETIME = F
I2C_CLK
x0.3+1
For example, when I2C clock is 48MHz, RISETIME =
48x0.3+1
Note: RISETIME[5:0] can be configured only when
I2CEN=0.