AT32F421 Series Reference Manual
2022.11.11 Page 57 Rev 2.02
POR/LVR reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No POR/LVR reset occurs
1: POR/LVR reset occurs.
NRST pin reset flag
Set by hardware. Cleared by writing to the RSTFC bit.
0: No NRST pin reset occurs
1: NRST pin reset occurs
Kept at its default value.
Reset flag clear
Cleared by writing 1 through software.
0: No effect
1: Clear the reset flag.
Kept at its default value.
LICK stable
0: LICK is not ready.
1: LICK is ready.
LICK enable
0: Disabled
1: Enabled
4.3.11 AHB peripheral reset register (CRM_AHBRST)
Access: 0 wait state, accessible by words, half-words and bytes.
Kept at its default value.
GPIOF reset
This bit is set or cleared by software.
0: Does not reset GPIOF
1: Reset GPIOF
Kept at its default value.
GPIOC reset
This bit is set or cleared by software.
0: Does not reset GPIOC
1: Reset GPIOC
GPIOB reset
This bit is set or cleared by software.
0: Does not reset GPIOB
1: Reset GPIOB
GPIOA reset
This bit is set or cleared by software.
0: Does not reset GPIOA
1: Reset GPIOA
Kept at its default value.
4.3.12 PLL configuration register (CRM_PLL)
PLL configuration enable
0: Common integer multiplication mode, which is done
by PLL_FREF and PLLMULT registers.
1: Flexible configuration mode, which is done by
PLL_MS/PLL_NS/PLL_FR registers.
Kept at its default value.
PLL input clock selection
This field is valid only if PLLCFGEN=0.
000: 3.9 ~ 5 MHz
001: 5.2 ~ 6.25 MHz
010: 7.8125 ~ 8.33 MHz
011: 8.33 ~ 12.5 MHz
100: 15.625 ~ 20.83 MHz
101: 20.83 ~ 31.25 MHz
110: Reserved
111: Reserved
Kept at its default value.
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