ARTERY AT32F421C8T7 - Control Register3 (USART_CTRL3)

AT32F421 Series Reference Manual
2022.11.11 Page 147 Rev 2.02
1: Clock is enabled.
Bit 10
CLKPOL
0x0
rw
Clock polarity
In synchronous mode or Smartcard mode, this bit is used
to select the polarity of the clock output on the clock pin in
idle state.
0: Clock output low
1: Clock output high
Bit 9
CLKPHA
0x0
rw
Clock phase
This bit is used to select the phase of the clock output on
the clock pin in synchronous mode or Smartcard mode.
0: Data capture is done on the first clock edge.
1: Data capture is done on the second clock edge.
Bit 8
LBCP
0x0
rw
Last bit clock pulse
This bit is used to select whether the clock pulse of the
last data bit transmitted is output on the clock pin in
synchronous mode.
0: The clock pulse of the last data bit is no output on the
clock pin.
1: The clock pulse of the last data bit is output on the clock
pin.
Bit 7
Reserved
0x0
resd
Keep at its default value.
Bit 6
BFIEN
0x0
rw
Brake frame interrupt enable
0: Disabled
1: Enabled
Bit 5
BFBN
0x0
rw
Brake frame bit num
This bit is used to select 11-bit or 10-bit brake frame.
0: 10-bit brake frame
1: 11-bit brake frame
Bit 4
Reserved
0x0
resd
Keep at its default value.
Bit 3: 0
ID
0x0
rw
USART identification
Configurable USART ID.
Note: These three bits (CLKPOL, CLKPHA and LBCP) cannot be changed while the transmission is
enabled.
12.12.6 Control register3 (USART_CTRL3)
Bit
Register
Reset value
Type
Description
Bit 31: 11
Reserved
0x000000
resd
Forced 0 by hardware.
Bit 10
CTSCFIEN
0x0
rw
CTSCF interrupt enable
0: Interrupt is disabled.
1: Interrupt is enabled.
Bit 9
CTSEN
0x0
rw
CTS enable
0: CTS is disabled.
1: CTS is enabled.
Bit 8
RTSEN
0x0
rw
RTS enable
0: RTS is disabled.
1: RTS is enabled.
Bit 7
DMATEN
0x0
rw
DMA transmitter enable
0: DMA transmitter is disabled.
1: DMA transmitter is enabled.
Bit 6
DMAREN
0x0
rw
DMA receiver enable
0: DMA receiver is disabled.
1: DMA receiver is enabled.
Bit 5
SCMEN
0x0
rw
Smartcard mode enable
0: Smartcard mode is disabled.