ARTERY AT32F421C8T7 - GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A; GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A; GPIO Bit Clear Register (Gpiox_Clr) (X=A; GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A

AT32F421 Series Reference Manual
2022.11.11 Page 90 Rev 2.02
6.3.9 GPIO multiplexed function low register (GPIOx_MUXL)
(x=A..H)
Address offset: 0x20
Reset value: 0x00000000
Bit
Register
Reset value
Type
Description
Bit
4y+3: 4y
MUXLy
0x0
rw
Multiplexed function select for GPIOx pin y (y=0…7)
This field is used to configure multiplexed function IOs.
0000: MUX0
0001: MUX1
0010: MUX2
0011: MUX3
0100: MUX4
0101: MUX5
0110: MUX6
0111: MUX7
1xxx: Reserved
6.3.10 GPIO multiplexed function high register (GPIOx_MUXH)
(x=A..H)
Bit
Register
Reset value
Type
Description
Bit
4y+3: 4y
MUXHy
0x0
rw
Multiplexed function select for GPIOx pin y (y=8…15)
This field is used to configure multiplexed function IOs
0000: MUX0
0001: MUX1
0010: MUX2
0011: MUX3
0100: MUX4
0101: MUX5
0110: MUX6
0111: MUX7
1xxx: Reserved
6.3.11 GPIO bit clear register (GPIOx_CLR) (x=A…H)
Bit
Register
Reset value
Type
Description
Bit 31: 16
Reserved
0x0000
resd
Kept at its default value.
Bit 15: 0
IOCB
0x0000
wo
GPIOx clear bit
The corresponding ODT register bit is cleared by writing
“1” to these bits. Otherwise, the corresponding ODT
register bit remains unchanged, which acts as ODT
register bit operations.
0: No action to the corresponding ODT bits
1: Clear the corresponding ODT bits
6.3.12 GPIO huge current control register (GPIOx_HDRV)
(x=A..H)
Bit
Register
Reset value
Type
Description
Bit 31: 16
Reserved
0x0000
resd
Kept at its default value.
Bit 15:0
HDRV
0x0000
rw
Huge sourcing/sinking strength control
0: Not active
1: GPIO is configured as maximum sourcing/sinking
strength