ARTERY AT32F421C8T7 - Flash Status Register (FLASH

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AT32F421 Series Reference Manual

2022.11.11 Page 74 Rev 2.02

5.8.4 Flash status register (FLASH_STS)

Bit

Abbr.

Reset value

Type

Description

Bit 31: 6

Reserved

0x0000000

resd

Kept at its default value

Bit 5

ODF

rw1c

Operation done flag

This bit is set by hardware when Flash memory

operations (program/erase) are complete. It is

cleared by writing “1”.

Bit 4

EPPERR

rw1c

Erase/program protection error

This bit is set by hardware when programming the

erase/program- protected Flash memory address. It

is cleared by writing “1”.

Bit 3

Reserved

resd

Kept at its default value.

Bit 2

PRGMERR

rw1c

Programming error

When the Flash programming address is in “non-erase”

state, this bit is set by hardware. It is cleared by writing

“1”.

Bit 1

Reserved

resd

Kept at its default value.

Bit 0

OBF

Operation busy flag

When this bit is set, it indicates that Flash memory

operation is in progress. It is cleared when operation is

complete.

Main Page

Table of Contents2
System Architecture25
Figure 1-1 AT32F421 Series Microcontrollers System Architecture26
System Overview27
ARM Cortex27
TM -M4 Processor27
Bit Band27
Figure 1-2 Internal Block Diagram of Cortex ® -M427
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a27
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B28
Table 1-1 Bit-Band Address Mapping in SRAM28
Interrupt and Exception Vectors29
Table 1-2 Bit-Band Address Mapping in the Peripheral Area29
Table 1-3 AT32F421 Series Vector Table29
System Tick (Systick)31
Reset31
Figure 1-5 Reset Process31
Figure 1-6 Example of MSP and PC Initialization32
List of Abbreviations for Registers33
Device Characteristics Information33
Flash Memory Size Register33
Device Electronic Signature33
Table 1-4 List of Abbreviations for Registers33
Table 1-5 List of Abbreviations for Registers33
Memory Resources34
Internal Memory Address Map34
Figure 2-1AT32F421 Address Mapping34
Flash Memory35
SRAM Memory35
Table 2-1 Flash Memory Organization (64 KB)35
Table 2-2 Flash Memory Organization (32 KB)35
Table 2-3 Flash Memory Organization (16 KB)35
Peripheral Address Map36
Table 2-4 Peripheral Boundary Address36
Power Control (PWC)39
Introduction39
Main Features39
Figure 3-1 Block Diagram of each Power Supply39
Por/Lvr40
Power Voltage Monitor (PVM)40
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform40
Power Domain41
Power Saving Modes41
Figure 3-3 PVM Threshold and Output41
PWC Registers43
Power Control Register (PWC_CTRL)43
Table 3-1 PW Register Map and Reset Values43
Power Control/Status Register (PWC_CTRLSTS)44
Power Control Register 2 (PWC_CTRL2)44
Clock and Reset Manage (CRM)45
Clock45
Clock Sources45
Figure 4-1 AT32F421 Clock Tree45
System Clock46
Peripheral Clock46
Clock Fail Detector47
Auto Step-By-Step System Clock Switch47
Internal Clock Output47
Interrupts47
Reset47
System Reset47
Battery Powered Domain Reset48
CRM Registers48
Figure 4-2 System Reset Circuit48
Table 4-1 CRM Register Map and Reset Values48
Clock Control Register (CRM_CTRL)49
Clock Configuration Register (CRM_CFG)50
Clock Interrupt Register (CRM_CLK INT)51
APB2 Peripheral Reset Register (CRM_APB2RST)52
APB1 Peripheral Reset Register1 (CRM_APB1RST)53
AHB Peripheral Clock Enable Register (CRM_AHBEN)53
APB2 Peripheral Clock Enable Register (CRM_APB2EN)54
APB1 Peripheral Clock Enable Register (CRM_APB1EN)55
Battery Powered Domain Control Register (CRM_BPDC)56
Control/Status Register (CRM_CTRLSTS)56
AHB Peripheral Reset Register (CRM_AHBRST)57
PLL Configuration Register (CRM_PLL)57
Additional Register (CRM_MISC1)58
Additional Register (CRM_MISC2)59
Embedded Flash Memory Controller (FLASH)60
FLASH Introduction60
Table 5-1 Flash Memory Architecture(64 K)60
Table 5-2 Flash Memory Architecture(32 K)60
Table 5-3 Flash Memory Architecture(16 K)60
Table 5-4 User System Data Area61
Flash Memory Operation62
Unlock/Lock62
Erase Operation62
Figure 5-1 Flash Memory Sector Erase Process63
Programming Operation64
Figure 5-2 Flash Memory Mass Erase Process64
Read Operation65
Main Flash Memory Extension Area65
Figure 5-3 Flash Memory Programming Process65
User System Data Area66
Unlock/Lock66
Erase Operation66
Figure 5-4 System Data Area Erase Process67
Programming Operation68
Figure 5-5 System Data Area Programming Process68
Read Operation69
Flash Memory Protection69
Access Protection69
Table 5-5 Flash Memory Access Limit69
Erase/Program Protection70
Read Access70
Special Functions70
Security Library Settings70
Boot Memory Used as Memory Extension Area71
CRC Verify72
Flash Memory Registers72
Table 5-6 Flash Memory Interface-Register Map and Reset Value72
Flash Performance Select Register (FLASH_PSR)73
Flash Unlock Register (FLASH_UNLOCK)73
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)73
Flash Status Register (FLASH_STS)74
Flash Control Register (FLASH_CTRL)75
Flash Address Register (FLASH_ADDR)76
User System Data Register (FLASH_USD)76
Erase/Program Protection Status Register (FLASH_EPPS)76
Flash Security Library Status Register 0 (SLIB_STS0)77
Flash Security Library Status Register1 (SLIB_STS1)77
Security Library Password Clear Register (SLIB_PWD_CLR)78
Security Library Additional Status Register (SLIB_MISC_STS)78
Flash CRC Address Register (FLASH_CRC_ARR)78
Flash CRC Control Register (FLASH_CRC_CTRL)79
Flash CRC Check Result Register (FLASH_CRC_CHKR)79
Security Library Password Setting Register (SLIB_SET_PWD)79
Security Library Address Setting Register (SLIB_SET_RANGE)79
Boot Memory Mode Setting Register (BTM_MODE_SET)81
Security Library Unlock Register (FLASH_UNLOCK)81
General-Purpose I/Os (Gpios)82
Introduction82
Functional Overview82
GPIO Structure82
GPIO Reset Status82
Figure 6-1 GPIO Basic Structure82
General-Purpose Input Configuration83
Analog Input/Output Configuration83
General-Purpose Output Configuration83
GPIO Port Protection83
IOMUX Structure84
Multiplexed Function Input Configuration84
Figure 6-2 IOMUX Structure84
IOMUX Function Input/Output85
Table 6-1 Multiplexed Function Configuration for Port a Using GPIO_A MUX* Register85
Table 6-2 Multiplexed Function Configuration for Port B Using GPIO_B MUX* Register86
Table 6-3 Multiplexed Function Configuration for Port F Using GPIO_F MUX* Register86
Peripheral Multiplexed Function Configuration87
IOMUX Map Priority87
External Interrupt/Wake-Up Lines87
GPIO Registers87
Table 6-4 Hardware Preemption87
Table 6-5 GPIO Register Map and Reset Values87
GPIO Configuration Register (Gpiox_Cfgr) (X=A88
GPIO Input Mode Register (Gpiox_Omode) (X=A88
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..h88
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..h88
GPIO Input Data Register (Gpiox_Idt) (X=A89
GPIO Output Data Register (Gpiox_Odt) (X= a89
GPIO Set/Clear Register (Gpiox_Scr) (X=A89
GPIO Write Protection Register (Gpiox_Wpr) (X=A89
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A90
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A90
GPIO Bit Clear Register (Gpiox_Clr) (X=A90
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A90
System Configuration Controller (SCFG)91
Introduction91
SCFG Registers91
SCFG Configuration Register1 (SCFG_CFG1)91
SCFG External Interrupt Configuration Register1 (SCFG_ EXINTC1)92
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)93
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)93
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)94
External Interrupt/Event Controller (EXINT)95
EXINT Introduction95
Function Overview and Configuration Procedure95
Figure 8-1 External Interrupt/Event Controller Block Diagram95
EXINT Registers96
Interrupt Enable Register (EXINT_INTEN)96
Event Enable Register (EXINT_EVTEN)96
Polarity Configuration Register1 (EXINT_ POLCFG1)96
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value96
Polarity Configuration Register2 (EXINT_ POLCFG2)97
Software Trigger Register (EXINT_ SWTRG)97
Interrupt Status Register (EXINT_ INTSTS)97
DMA Controller (DMA)98
Introduction98
Main Features98
Functional Overview98
DMA Configuration98
Figure 9-1 DMA Block Diagram98
Handshake Mechanism99
Arbiter99
Figure 9-2 Re-Arbitrate after Request/Acknowledge99
Programmable Data Transfer Width100
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word100
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word100
Figure 9-5 PWIDTH: Word, MWIDTH: Byte100
Errors101
Interrupts101
Fixed DMA Request Mapping101
Table 9-1 DMA Error Event101
Table 9-2 DMA Interrupt Requests101
Table 9-3 DMA Requests for each Channel101
DMA Registers102
Table 9-4 DMA Register Map and Reset Value102
DMA Interrupt Status Register (DMA_STS)103
DMA Interrupt Flag Clear Register (DMA_CLR)104
DMA Channel-X Configuration Register (Dma_Cxctrl)105
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X = 1106
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr) (X = 1106
DMA Channel-X Memory Address Register (Dma_Cxmaddr) (X = 1106
CRC Calculation Unit (CRC)107
CRC Introduction107
CRC Registers107
Data Register (CRC_DT)107
Common Data Register (CRC_CDT)107
Table 10-1 CRC Register Map and Reset Value107
Control Register (CRC_CTRL)108
Initialization Register (CRC_IDT)108
C Interface109
I 2 C Introduction109
I 2 C Main Features109
I 2 C Functional Overview109
Figure 11-1 I C Bus Protocol109
I 2 C Interface110
Figure 11-2 I C Function Block Diagram110
C Slave Communication Flow111
Figure 11-3 Transfer Sequence of Slave Transmitter112
Figure 11-4 Transfer Sequence of Slave Receiver113
C Master Communication Flow114
Figure 11-5 Transfer Sequence of Master Transmitter114
Figure 11-6 Transfer Sequence of Master Receiver116
Figure 11-7 Transfer Sequence of Master Receiver When N>2117
Figure 11-8 Transfer Sequence of Master Receiver When N=2118
Figure 11-9 Transfer Sequence of Master Receiver When N=1119
Data Transfer Using DMA120
Smbus121
C Interrupt Requests122
C Debug Mode123
I 2 C Registers123
Control Register1 (I2C_CTRL1)123
Table 11-1 I 2 C Register Map and Reset Values123
Control Register2 (I2C_CTRL2)124
Own Address Register1 (I2C_OADDR1)125
Own Address Register2 (I2C_OADDR2)125
Data Register (I2C_DT)126
Status Register1 (I2C_STS1)126
Status Register2 (I2C_STS2)128
Clock Control Register (I2C_ CLKCTRL)129
Clock Rise Time Register (I2C_TMRISE)129
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)130
USART Introduction130
Figure 12-1 USART Block Diagram130
Full-Duplex/Half-Duplex Selector132
Mode Selector132
Introduction132
Configuration Procedure132
Figure 12-2 BFF and FERR Detection in LIN Mode133
Figure 12-3 Smartcard Frame Format133
Figure 12-4 Irda DATA(3/16) - Normal Mode134
Figure 12-5 Hardware Flow Control134
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection135
Figure 12-7 8-Bit Format USART Synchronous Mode135
USART Frame Format and Configuration136
Figure 12-8 Word Length136
DMA Transfer Introduction137
Transmission Using DMA137
Reception Using DMA137
Figure 12-9 Stop Bit Configuration137
Baud Rate Generation138
Introduction138
Configuration138
Table 12-1 Baud Rate Calculation Error138
Transmitter139
Transmitter Introduction139
Transmitter Configuration139
Figure 12-10 TDC/TDBE Behavior When Transmitting139
Receiver140
Receiver Introduction140
Receiver Configuration140
Start Bit and Noise Detection141
Table 12-2 Data Sampling over Start Bit and Noise Detection141
Table 12-3 Data Sampling over Valid Data and Noise Detection141
Tx/Rx Swap142
Interrupt Requests142
Figure 12-11 Data Sampling for Noise Detection142
Figure 12-12 Tx/Rx Swap142
Table 12-4 USART Interrupt Request142
I/O Pin Control143
USART Registers143
Figure 12-13 USART Interrupt Map Diagram143
Table 12-5 USART Register Map and Reset Value143
Status Register (USART_STS)144
Data Register (USART_DT)145
Baud Rate Register (USART_BAUDR)145
Control Register1 (USART_CTRL1)145
Control Register2 (USART_CTRL2)146
Control Register3 (USART_CTRL3)147
Guard Time and Divider Register (USART_GDIV)148
Serial Peripheral Interface (SPI)149
SPI Introduction149
Functional Overview149
SPI Description149
Figure 13-1 SPI Block Diagram149
Full-Duplex/Half-Duplex Selector150
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection150
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode150
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode151
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode151
Chip Select Controller152
SPI_SCK Controller152
Crc152
DMA Transfer153
Transmitter154
Receiver154
Motorola Mode155
Figure 13-6 Master Full-Duplex Communications155
Figure 13-7 Slave Full-Duplex Communications156
Figure 13-8 Slave Full-Duplex Communications156
Figure 13-9 Slave Half-Duplex Receive156
Interrupts157
Figure 13-10 Slave Half-Duplex Transmit157
Figure 13-11 Master Half-Duplex Receive157
Figure 13-12 SPI Interrupts157
IO Pin Control158
Precautions158
I2S Functional Description158
S Introduction158
Figure 13-13 I 2 S Block Diagram158
Operation Mode Selector159
Figure 13-14 I 2 S Slave Device Transmission159
Figure 13-15 I 2 S Slave Device Reception159
Audio Protocol Selector160
Figure 13-16 I 2 S Master Device Transmission160
Figure 13-17 I 2 S Master Device Reception160
I2S_CLK Controller161
Figure 13-18 CK & MCK Source in Master Mode162
Table 13-1 Audio Frequency Precision Using System Clock162
DMA Transfer163
Transmitter/Receiver164
I2S Communication Timings165
Interrupts165
IO Pin Control165
Figure 13-19 Audio Standard Timings165
Figure 13-20 I 2 S Interrupts165
SPI Registers166
SPI Control Register1 (SPI_CTRL1)166
Mode166
Table 13-2 SPI Register Map and Reset Value166
SPI Control Register2 (SPI_CTRL2)167
SPI Status Register (SPI_STS)168
SPI Data Register (SPI_DT)168
SPICRC Register (SPI_CPOLY)168
Mode)168
Spirxcrc Register (SPI_RCRC)169
Mode)169
Spitxcrc Register (SPI_TCRC)169
SPI_I2S Configuration Register (SPI_I2SCTRL)169
SPI_I2S Prescaler Register (SPI_I2SCLKP)170
Timer171
Table 14-1 TMR Functional Comparison171
General-Purpose Timer (TMR6)172
TMR6 Introduction172
TMR6 Main Features172
TMR6 Functional Overview172
Count Clock172
Counting Mode172
Figure 14-1 Basic Timer Block Diagram172
Figure 14-2 Counter Timing Diagram, CK_INT Divided by 1172
Debug Mode173
Figure 14-3 Counter Structure173
Figure 14-4 Overflow Event When PRBEN=0173
Figure 14-5 Overflow Event When PRBEN=1173
Figure 14-6 Counter Timing Diagram, Internal Clock Divided by 4173
TMR6 Registers174
Table 14-2 TMR6 Register Map and Reset Value174
TMR6 Control Register1 (Tmrx_Ctrl1)175
TMR6 Control Register2 (Tmrx_Ctrl2)175
TMR6 Dma/Interrupt Enable Register (Tmrx_Iden)175
TMR6 Interrupt Status Register (Tmrx_Ists)176
TMR6 Software Event Register (Tmrx_Swevt)176
TMR6 Counter Value (Tmrx_Cval)176
TMR6 Division (Tmrx_Div)176
TMR6 Period Register (Tmrx_Pr)176
General-Purpose Timer (TMR3)177
TMR3 Introduction177
TMR3 Main Features177
TMR3 Functional Overview177
Count Clock177
Figure 14-7 Block Diagram of General-Purpose Timer177
Figure 14-8 Count Clock Block Diagram178
Figure 14-9 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16178
Figure 14-10 Block Diagram of External Clock Mode a179
Figure 14-11 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0179
Figure 14-12 Block Diagram in External Clock Mode B179
Figure 14-13 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0180
Figure 14-14 Counter Timing with Prescaler Value Changing from 1 to 4180
Table 14-3 TMR3 Internal Trigger Connection180
Counting Mode181
Figure 14-15 Counter Structure181
Figure 14-16 Overflow Event When PRBEN=0181
Figure 14-17 Overflow Event When PRBEN=1182
Figure 14-18 Counter Timing Diagram, Internal Clock Divided by 4182
Figure 14-19 Counter Timing Diagram, Internal Clock Divided by 1, Tmrx_Pr=0X32183
Figure 14-20 Encoder Mode Structure183
TMR Input Function184
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)184
Table 14-4 Counting Direction Versus Encoder Signals184
Figure 14-22 Input/Output Channel 1 Main Circuit185
Figure 14-23 Channel 1 Input Stage185
TMR Output Function186
Figure 14-24 PWM Input Mode Configuration186
Figure 14-25 PWM Input Mode186
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)187
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value188
Figure 14-28 Upcounting Mode and PWM Mode a188
Figure 14-29 Up/Down Counting Mode and PWM Mode a188
Figure 14-30 One-Pulse Mode189
Figure 14-31 Clearing Cxoraw(PWM Mode A) by EXT Input189
TMR Synchronization190
Figure 14-32 Example of Reset Mode190
Figure 14-33 Example of Suspend Mode190
Figure 14-34 Example of Trigger Mode190
Figure 14-35 Master/Slave Timer Connection191
Figure 14-36 Using Master Timer to Start Slave Timer191
Debug Mode192
TMR3 Registers192
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger192
Table 14-5 TMR3 Register Map and Reset Value192
Control Register1 (TMR3_CTRL1)193
Control Register2 (TMR3_CTRL2)194
Slave Timer Control Register (TMR3_STCTRL)194
Dma/Interrupt Enable Register (TMR3_IDEN)195
Interrupt Status Register (TMR3_ISTS)196
Software Event Register (TMR3_SW EVT)197
Channel Mode Register1 (Tmrx_Cm1)197
Channel Mode Register2 (TMR3_CM2)199
Channel Control Register (TMR3_CCTRL)200
Counter Value (TMR3_CVAL)200
Table 14-6 Standard Cxout Channel Output Control Bit200
Division Value (TMR3_DIV)201
Period Register (TMR3_PR)201
Channel 1 Data Register (TMR3_C1DT)201
Channel 2 Data Register (TMR3_C2DT)201
Channel 3 Data Register (TMR3_C3DT)201
Channel 4 Data Register (TMR3_C4DT)202
DMA Control Register (TMR3_DMACTRL)202
DMA Data Register (TMR3_DMADT)202
General-Purpose Timer (TMR14)203
TMR14 Introduction203
TMR14 Main Features203
TMR14 Functional Overview203
Count Clock203
Figure 14-38 Block Diagram of General-Purpose TMR14203
Figure 14-39 Count Clock203
Figure 14-40 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16203
Counting Mode204
Figure 14-41 Counter Timing with Prescaler Value Changing from 1 to 4204
Figure 14-42 Counter Structure204
TMR Input Function205
Figure 14-43 Overflow Event When PRBEN=0205
Figure 14-44 Overflow Event When PRBEN=1205
Figure 14-45 Input/Output Channel 1 Main Circuit205
TMR Output Function206
Figure 14-46 Channel 1 Input Stage206
Figure 14-47 Capture/Compare Channel Output Stage (Channel 1)206
Debug Mode207
TMR14 Registers207
Figure 14-48 C1ORAW Toggles When Counter Value Matches the C1DT Value207
Figure 14-49 Upcounting Mode and PWM Mode a207
Control Register1 (TMR14_CTRL1)208
Interrupt Enable Register (TMR14_IDEN)208
Interrupt Status Register (TMR14_ISTS)208
Table 14-7 TMR14 Register Map and Reset Value208
Software Event Register (TMR14_SWEVT)209
Channel Mode Register1 (TMR14_CM1)209
Channel Control Register (TMR14_CCTRL)212
Counter Value (TMR14_CVAL)212
Division Value (TMR14_DIV)212
Period Register (TMR14_PR)212
Channel 1 Data Register (TMR14_C1DT)212
Table 14-8 Standard Cxout Channel Output Control Bit212
Channel Input Remap Register (TMR14_RMP)213
General-Purpose Timer (TMR15)214
TMR15 Introduction214
TMR15 Main Features214
TMR15 Functional Overview214
Count Clock214
Figure 14-50 Block Diagram of General-Purpose TMR15214
Figure 14-51 Count Clock214
Figure 14-52 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16215
Figure 14-53 Block Diagram of External Clock Mode a215
Counting Mode216
Figure 14-54 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0216
Figure 14-55 Counter Timing with Prescaler Value Changing from 1 to 4216
Table 14-9 TMR15 Internal Trigger Connection216
Figure 14-56 Counter Structure217
Figure 14-57 Overflow Event When PRBEN=0217
Figure 14-58 Overflow Event When PRBEN=1217
TMR Input Function218
Figure 14-59 OVFIF When RPR=2218
Figure 14-60 Input/Output Channel 1 Main Circuit218
Figure 14-61 Channel 1 Input Stage219
TMR Output Function220
Figure 14-62 PWM Input Mode Configuration220
Figure 14-63 PWM Input Mode220
Figure 14-64 Channel 1 Output Stage220
Figure 14-65 Channel 2 Output Stage221
Figure 14-66 C1ORAW Toggles When Counter Value Matches the C1DT Value222
Figure 14-67 Upcounting Mode and PWM Mode a222
Figure 14-68 One-Pulse Mode223
TMR Brake Function224
Figure 14-69 Complementary Output with Dead-Time Insertion224
TMR Synchronization225
Figure 14-70 TMR Control Output225
Figure 14-71 Example of TMR Brake Function225
Debug Mode226
Figure 14-72 Example of Reset Mode226
Figure 14-73 Example of Suspend Mode226
Figure 14-74 Example of Trigger Mode226
TMR15 Registers227
Control Register1 (TMR15_CTRL1)227
Table 14-10 TMR15 Register Map and Reset Value227
Control Register2 (TMR15_CTRL2)228
TMR15 Slave Timer Control Register (TMR15_STCTRL)228
TMR15 Dma/Interrupt Enable Register (TMR15_IDEN)229
TMR15 Interrupt Status Register (TMR15_ISTS)230
TMR15 Software Event Register (TMR15_SW EVT)231
TMR15 Channel Mode Register1 (TMR15_CM1)231
TMR15 Channel Control Register (TMR15_CCTRL)234
Table 14-11 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function235
TMR15 Counter Value (TMR15_CVAL)236
TMR15 Division Value (TMR15_DIV)236
TMR15 Period Register (TMR15_PR)236
TMR15 Repetition Period Register (TMR15_RPR)236
TMR15 Channel 1 Data Register (TMR15_C1DT)236
TMR15 Channel 2 Data Register (TMR15_C2DT)236
TMR15 Brake Register (TMR15_BRK)237
TMR15 DMA Control Register (TMR15_DMACTRL)238
TMR15 DMA Data Register (TMR15_DMADT)238
General-Purpose Timer (TMR16 and TMR17)239
TMR16 and TMR17 Introduction239
TMR16 and TMR17 Main Features239
TMR16 and TMR17 Functional Overview239
Count Clock239
Figure 14-75 Block Diagram of General-Purpose TMR16 and TMR17239
Figure 14-76 Count Clock239
Counting Mode240
Figure 14-77 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16240
Figure 14-78 Counter Structure240
TMR Input Function241
Figure 14-79 Overflow Event When PRBEN=0241
Figure 14-80 Overflow Event When PRBEN=1241
Figure 14-81 OVFIF When RPR=2241
TMR Output Function242
Figure 14-82 Input/Output Channel 1 Main Circuit242
Figure 14-83 Channel 1 Input Stage242
Figure 14-84 Channel 1 Output Stage242
Figure 14-85 C1ORAW Toggles When Counter Value Matches the C1DT Value244
Figure 14-86 Upcounting Mode and PWM Mode a244
Figure 14-87 One-Pulse Mode244
TMR Brake Function245
Figure 14-88 Complementary Output with Dead-Time Insertion245
Debug Mode246
TMR16 and TMR17 Registers246
Figure 14-89 TMR Output Control246
Figure 14-90 Example of TMR Brake Function246
Table 14-12 TMR16 and TMR17 Register Map and Reset Value246
TMR16 and TMR17 Control Register1 (Tmrx_Ctrl1)247
TMR16 and TMR17 Control Register2 (Tmrx_Ctrl2)247
TMR16 and TMR17 Dma/Interrupt Enable Register (Tmrx_Id248
TMR16 and TMR17 Interrupt Status Register (Tmrx_Ists)248
TMR16 and TMR17 Software Event Register (Tmrx_Swevt)249
TMR16 and TMR17 Channel Mode Register1 (Tmrx_Cm1)249
TMR16 and TMR17 Channel Control Register (Tmrx_Cctrl)252
Table 14-13 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function252
TMR16 and TMR17 Counter Value (Tmrx_Cval)253
TMR16 and TMR17 Division Value (Tmrx_Div)253
TMR16 and TMR17 Period Register (Tmrx_Pr)253
TMR16 and TMR17 Repetition Period Register (Tmrx_Rpr)253
TMR16 and TMR17 Channel 1 Data Register (Tmrx_C1Dt)253
TMR16 and TMR17 Brake Register (Tmrx_Brk)254
TMR16 and TMR17 DMA Control Register (Tmrx_Dmactrl)255
TMR16 and TMR17 DMA Data Register (Tmrx_Dmadt)255
Advanced-Control Timers (TMR1)256
TMR1 Introduction256
TMR1 Main Features256
TMR1 Functional Overview256
Count Clock256
Figure 14-91 Block Diagram of Advanced-Control Timer256
Figure 14-92 Count Clock257
Figure 14-93 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16257
Figure 14-94 Block Diagram of External Clock Mode a258
Figure 14-95 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0258
Figure 14-96 Block Diagram of External Clock Mode B259
Figure 14-97 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0259
Table 14-14 TMR1 Internal Trigger Connection259
Counting Mode260
Figure 14-98 Counter Timing with Prescaler Value Changing from 1 to 4260
Figure 14-99 Counter Structure260
Figure 14-100 Overflow Event When PRBEN=0261
Figure 14-101 Overflow Event When PRBEN=1261
Figure 14-102 Counter Timing Diagram with Internal Clock Divided by 4261
Figure 14-103 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32262
Figure 14-104 OVFIF in Upcounting Mode and Up/Down Counting Mode262
Figure 14-105 Encoder Mode Structure263
Table 14-15 Counting Direction Versus Encoder Signals263
TMR Input Function264
Figure 14-106 Example of Encoder Interface Mode C264
Figure 14-107 Input/Output Channel 1 Main Circuit264
Figure 14-108 Channel 1 Input Stage265
TMR Output Function266
Figure 14-109 PWM Input Mode Configuration266
Figure 14-110 PWM Input Mode266
Figure 14-111 Output Stage for Channel 1 to 3266
Figure 14-112 Output Stage for Channel 4267
Figure 14-113 C1ORAW Toggles When Counter Value Matches the C1DT Value268
Figure 14-114 Upcounting Mode and PWM Mode a268
Figure 14-115 Up/Down Counting Mode and PWM Mode a268
Figure 14-116 One-Pulse Mode269
Figure 14-117 Clearing Cxoraw(PWM Mode A) by EXT Input269
TMR Brake Function270
Figure 14-118 Complementary Output with Dead-Time Insertion270
TMR Synchronization271
Figure 14-119 TMR Output Control271
Figure 14-120 Example of TMR Brake Function271
Debug Mode272
Figure 14-121 Example of Reset Mode272
Figure 14-122 Example of Suspend Mode272
Figure 14-123 Example of Trigger Mode272
TMR1 Registers273
TMR1 Control Register1 (TMR1_CTRL1)273
Table 14-16 TMR1 Register Map and Reset Value273
TMR1 Control Register2 (TMR1_CTRL2)275
TMR1 Slave Timer Control Register (TMR1_STCTRL)275
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)276
TMR1 Interrupt Status Register (TMR1_ISTS)278
TMR1 Software Event Register (TMR1_SWEVT)279
TMR1 Channel Mode Register1 (TMR1_CM1)279
TMR1 Channel Mode Register2 (TMR1_CM2)281
TMR1 Channel Control Register (TMR1_CCTRL)282
Table 14-17 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function283
TMR1 Counter Value (TMR1_CVAL)284
TMR1 Division Value (TMR1_DIV)284
TMR1 Period Register (TMR1_PR)284
TMR1 Repetition Period Register (TMR1_RPR)284
TMR1 Channel 1 Data Register (TMR1_C1DT)284
TMR1 Channel 2 Data Register (TMR1_C2DT)284
TMR1 Channel 3 Data Register (TMR1_C3DT)285
TMR1 Channel 4 Data Register (TMR1_C4DT)285
TMR1 Brake Register (TMR1_BRK)285
TMR1 DMA Control Register (TMR1_DMACTRL)286
TMR1 DMA Data Register (TMR1_DMADT)286
Window Watchdog Timer (WWDT)287
WWDT Introduction287
WWDT Main Features287
WWDT Functional Overview287
Figure 15-1 Window Watchdog Block Diagram287
Debug Mode288
WWDT Registers288
Control Register (WWDT_CTRL)288
Figure 15-2 Window Watchdog Timing Diagram288
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz288
Table 15-2 WWDT Register Map and Reset Value288
Configuration Register (WWDT_CFG)289
Status Register (WWDT_STS)289
Watchdog Timer (WDT)290
WDT Introduction290
WDT Main Features290
WDT Functional Overview290
Figure 16-1 WDT Block Diagram290
Debug Mode291
WDT Registers291
Command Register (WDT_CMD)291
Divider Register (WDT_DIV)291
Table 16-1 WDT Timeout Period (Lick=40Khz)291
Table 16-2 WDT Register and Reset Value291
Reload Register (WDT_RLD)292
Status Register (WDT_STS)292
Enhanced Real-Time Clock (ERTC)293
ERTC Introduction293
ERTC Main Features293
ERTC Functional Overview293
ERTC Clock293
Figure 17-1 ERTC Block Diagram293
ERTC Initialization294
Table 17-1 ERTC Register Configuration294
ERTC Calibration296
Time Stamp296
Tamper Detection297
Multiplexed Function Output297
ERTC Wakeup297
ERTC Registers298
ERTC Time Register (ERTC298
Table 17-2 ERTC Low-Power Mode Wakeup298
Table 17-3 Interrupt Control Bits298
Table 17-4 ERTC Register Map and Reset Values298
ERTC Date Register (ERTC_DATE)299
ERTC Control Register (ERTC_CTRL)299
ERTC Initialization and Status Register (ERTC_STS)300
ERTC Divider Register (ERTC_DIV)301
ERTC Alarm Clock a Register (ERTC_ALA)301
ERTC Write Protection Register (ERTC_WP)302
ERTC Subsecond Register (ERTC_SBS)302
ERTC Time Adjustment Register (ERTC_TADJ)302
ERTC Time Stamp Time Register (ERTC_TSTM)302
ERTC Time Stamp Date Register (ERTC_TSDT)303
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)303
ERTC Smooth Calibration Register (ERTC_SCAL)303
ERTC Tamper Configuration Register (ERTC_TAMP)303
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)305
ERTC Battery Powered Domain Data Register (Ertc_Bprx)305
Analog-To-Digital Converter (ADC)306
ADC Introduction306
ADC Main Features306
ADC Structure306
ADC Functional Overview307
Channel Management307
Figure 18-1 ADC1 Block Diagram307
Internal Temperature Sensor308
Internal Reference Voltage308
ADC Operation Process308
Power-On and Calibration308
Figure 18-2 ADC Basic Operation Process308
Trigger309
Figure 18-3 ADC Power-On and Calibration309
Table 18-1 Trigger Sources for ADC1309
Sampling and Conversion Sequence310
Conversion Sequence Management310
Sequence Mode310
Automatic Preempted Group Conversion Mode310
Figure 18-4 Sequence Mode310
Repetition Mode311
Partition Mode311
Figure 18-5 Preempted Group Auto Conversion Mode311
Figure 18-6 Repetition Mode311
Data Management312
Data Alignment312
Data Read312
Figure 18-7 Partition Mode312
Figure 18-8 Data Alignment312
Voltage Monitoring313
Status Flag and Interrupts313
ADC Registers313
Table 18-2 ADC Register Map and Reset Values313
ADC Status Register (ADC_STS)314
ADC Control Register1 (ADC_CTRL1)314
ADC Control Register2 (ADC_CTRL2)315
ADC Sampling Time Register 1 (ADC_SPT1)317
ADC Sampling Time Register 2 (ADC_SPT2)318
ADC Voltage Monitor High Threshold Register (ADC_VWHB)320
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)320
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)321
ADC Ordinary Sequence Register 2 (ADC_OSQ2)321
ADC Ordinary Sequence Register 3 (ADC_OSQ3)321
ADC Preempted Sequence Register (ADC_ PSQ)322
ADC Preempted Data Register X (ADC_ Pdtx) (X=1322
ADC Ordinary Data Register (ADC_ ODT)322
Comparator (COMP)323
COMP Introduction323
Main Features323
Interrupt Management323
Figure 19-1 Block Diagram of Comparator323
Design Tips324
Functional Overview324
Analog Comparator324
Glitch Filter325
CMP Registers325
Figure 19-2 Glitch Filter Timing When H_PULSE_CNT=1 and L_PULSE_CNT =0325
Figure 19-3 Glitch Filter Timing When H_PULSE_CNT=2 and L_PULSE_CNT =1325
Table 19-1 CMP Register Map and Reset Values325
Comparator Control and Status Register 1 (COMP_CTRLSTS)326
Glitch Filter Enable Register (G_FILTER_EN)327
Glitch Filter High Pulse Count (HIGH-PULSE)327
Glitch Filter Low Pulse Count (LOW-PULSE)328
Operational Amplifer (OPA)329
Introduction329
Main Features329
Functional Description329
Infrared Timer (IRTMR)331
Figure 21-1 IRTMR Block Diagram331
Debug (DEBUG)332
Debug Introduction332
Debug and Trace332
I/O Pin Control332
DEBUG Registers332
Table 22-1 DEBUG Register Address and Reset Value332
DEBUG Device ID (DEBUG_IDCODE)333
DEBUG Control Register (DEBUG_CTRL)334
Revision History336

ARTERY AT32F421C8T7 - Flash Status Register (FLASH_STS)

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