ARTERY AT32F421C8T7 - Control Register2 (I2 C_CTRL2)

AT32F421 Series Reference Manual
2022.11.11 Page 124 Rev 2.02
Bit 9
GENSTOP
0x0
rw
Generate stop condition
This bit is set or cleared by software. It is cleared when a
Stop condition is detected. It is set by hardware when a
timeout error is detected.
0: No Stop condition is generated.
1: Stop condition is generate.
The salve releases the SCL and SDA lines when this bit
is set in slave mode.
Bit 8
GENSTART
0x0
rw
Generate start condition
This bit is set or cleared by software. It is cleared when a
Start condition is sent.
0: No Start condition is generated.
1: Start condition is generated.
Bit 7
STRETCH
0x0
rw
Clock stretching mode
0: Enabled
1: Disabled
Note: This feature applies to slave mode only.
Bit 6
GCAEN
0x0
rw
General call address enable
0: Enabled
1: Disabled
Bit 5
PECEN
0x0
rw
PEC calculation enable
0: Disabled
1: Enabled
Bit 4
ARPEN
0x0
rw
SMBus address resolution protocol enable
0: Disabled
1: Enabled
SMBus host: response to host address 0001000x
SMBus slave: response to default device address
0001100x
Bit 3
SMBMODE
0x0
rw
SMBus device mode
0: SMBus slave
1: SMBus host
Bit 2
Reserved
0x0
resd
Forced to be 0 by hardware.
Bit 1
PERMODE
0x0
rw
I
2
C peripheral mode
0: I
2
C mode
1: SMBus mode
Bit 0
I2CEN
0x0
rw
I
2
C peripheral enable
0: Disabled
1: Enabled
All bits are cleared as I2CEN=0 at the end of the
communication.
In master mode, this bit must not be cleared before the
end of the communication.
Note: When the GENSTART, GENSTP or PECTEN bit is set, the I2C_CTRL1 cannot be written by
software until the corresponding bit has been cleared by hardware, otherwise, a second GENSTART,
GENSTP or PECTEN request may be set.
11.5.2 Control register2 (I2C_CTRL2)
Bit
Register
Reset value
Type
Description
Bit 15: 13
Reserved
0x0
resd
Forced to be 0 by hardware.
Bit 12
DMAEND
0x0
rw
End of DMA transfer
0: The next DMA transfer is no the last one.
1: The next DMA transfer is the last one.
Bit 11
DMAEN
0x0
rw
DMA transfer enable
0: Disabled