ARTERY AT32F421C8T7 - TMR1 Channel Control Register (TMR1_CCTRL)

AT32F421 Series Reference Manual
2022.11.11 Page 282 Rev 2.02
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C3EN=’0’:
00: Output
01: Input, C3IN is mapped on C3IFP3
10: Input, C3IN is mapped on C4IFP3
11: Input, C3IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Input capture mode:
Bit
Register
Reset value
Type
Description
Bit 15: 12
C4DF
0x0
rw
Channel 4 digital filter
Bit 11: 10
C4IDIV
0x0
rw
Channel 4 input divider
Bit 9: 8
C4C
0x0
rw
Channel 4 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C4EN=’0’:
00: Output
01: Input, C4IN is mapped on C4IFP4
10: Input, C4IN is mapped on C3IFP4
11: Input, C4IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Bit 7: 4
C3DF
0x0
rw
Channel 3 digital filter
Bit 3: 2
C3IDIV
0x0
rw
Channel 3 input divider
Bit 1:0
C3C
0x0
rw
Channel 3 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C3EN=’0’:
00: Output
01: Input, C3IN is mapped on C3IFP3
10: Input, C3IN is mapped on C4IFP3
11: Input, C3IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
14.6.4.9 TMR1 Channel control register (TMR1_CCTRL)
Bit
Register
Reset value
Type
Description
Bit 15: 14
Reserved
0x0
resd
Kept its default value.
Bit 13
C4P
0x0
rw
Channel 4 polarity
Please refer to C1P description.
Bit 12
C4EN
0x0
rw
Channel 4 enable
Please refer to C1EN description.
Bit 11
C3CP
0x0
rw
Channel 3 complementary polarity
Please refer to C1P description.
Bit 10
C3CEN
0x0
rw
Channel 3 complementary enable
Please refer to C1EN description.
Bit 9
C3P
0x0
rw
Channel 3 polarity
Please refer to C1P description.
Bit 8
C3EN
0x0
rw
Channel 3 enable
Please refer to C1EN description.
Bit 7
C2CP
0x0
rw
Channel 2 complementary polarity
Please refer to C1P description.
Bit 6
C2CEN
0x0
rw
Channel 2 complementary enable
Please refer to C1EN description.
Bit 5
C2P
0x0
rw
Channel 2 polarity
Please refer to C1P description.
Bit 4
C2EN
0x0
rw
Channel 2 enable
Please refer to C1EN description.
Bit 3
C1CP
0x0
rw
Channel 1 complementary polarity
0: C1COUT is active high.
1: C1COUT is active low.
Bit 2
C1CEN
0x0
rw
Channel 1 complementary enable
0: Output is disabled.
1: Output is enabled.
Bit 1
C1P
0x0
rw
Channel 1 polarity