AT32F421 Series Reference Manual
2022.11.11 Page 286 Rev 2.02
TMR1_BRK: DTC, BRKEN, BRKV and AOEN
TMR1_CTRL2: CxIOS and CxCIOS
10: Write protection level 2. The following bits and all bits
in level 3 are write protected:
TMR1_CCTRL: CxP and CxCP
TMR1_BRK: FCSODIS and FCSOEN
11: Write protection level 1. The following bits and all bits
in level 2 are write protected:
TMR1_CMx: C2OCTRL and C2OBEN
Note: Once WPC>0, its content remains frozen until the
next system reset.
Dead-time configuration
This field defines the duration of the dead-time insertion.
The 3-bit MSB of DTC[7: 0] is used for function
selection:
0xx: DT = DTC [7: 0] * TDTS
10x: DT = (64+ DTC [5: 0]) * TDTS * 2
110: DT = (32+ DTC [4: 0]) * TDTS * 8
111: DT = (32+ DTC [4: 0]) * TDTS * 16
Note: Based on lock configuration, AOEN, BRKV, BRKEN, FCSODIS, FCSOEN and DTC[7:0] can all
be write protected. Thus it is necessary to configure write protection when writing to the
TMRx_BRK register for the first time.
14.6.4.19 TMR1 DMA control register (TMR1_DMACTRL)
Kept at its default value.
DMA transfer bytes
This field defines the number of DMA transfers:
00000: 1 byte 00001: 2 bytes
00010: 3 bytes 00011: 4 bytes
...... ......
10000: 17 bytes 10001: 18 bytes
Kept at its default value.
DMA transfer address offset
ADDR is defined as an offset starting from the address
of the TMRx_CTRL1 register:
00000: TMRx_CTRL1
00001: TMRx_CTRL2
00010: TMRx_STCTRL
......
14.6.4.20 TMR1 DMA data register (TMR1_DMADT)
DMA data register
A write/read operation to the DMADT register accesses
any TMR register located at the following address:
TMRx peripheral address + ADDR*4 to TMRx peripheral
address + ADDR*4 + DTB*4
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