AT32F421 Series Reference Manual
2022.11.11 Page 294 Rev 2.02
The ck_a is used for subsecond update, while the ck_b is used for calendar update and periodic
autowakeup. The clock frequency of ck_a and ck_b can be obtained from the following equation:
F
ck_a
=
To obtain ck_b with frequency of 1 Hz, DIVA=127, DIVB=255, and 32.768 kHz LEXT should be used.
This ck_b is then used for calendar update.
17.3.2 ERTC initialization
ERTC register write protection
After a power-on reset, all ERTC registers are write protected except ERTC_STS[14:8], ERTC_TAMP
and ERTC_BPRx registers. Such protection mechanism is not affected by the system reset. The ERTC
registers can be written only after write protection is unlocked.
To unlock the write protection of ERTC registers, the steps below should be respected:
1. Enable power interface clock by setting PWCEN=1 in the CRM_APB1EN register
2. Unlock write protection of the battery powered domain by setting BPWEN=1 in the PWC_CTRL
register
3. Write 0xCA and 0x53 to the ERTC_WP register in sequence. Writing an incorrect key will activate
the write protection again.
Table 17-1 lists the ERTC registers that can be configured only after the write protection is unlocked and
when the initialization mode is entered.
Table 17-1 ERTC register configuration
Clock and calendar initialization
After the register write protection is unlocked, follow the procedure below for clock and calendar
initialization:
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