ARTERY AT32F421C8T7 - Power Control;Status Register (PWC_CTRLSTS); Power Control Register 2 (PWC_CTRL2)

AT32F421 Series Reference Manual
2022.11.11 Page 44 Rev 2.02
3.7.2 Power control/status register (PWC_CTRLSTS)
Unlike a standard APB read, an additional APB cycles are needed to read this register.
Bit
Name
Reset value
Type
Description
Bit 31: 15
Reserved
0x000000
resd
Kept at its default value.
Bit 14
SWPEN7
0x0
rw
Standby wake-up pin 7 enable
0: Disabled (this pin is used for general-purpose I/O)
1: Enabled (this pin is forced in input pull-down mode, and
no longer used for general-purpose I/O)
Note: This bit is cleared by hardware after system reset.
Bit 13
SWPEN6
0x0
rw
Standby wake-up pin 6 enable
0: Disabled (this pin is used for general-purpose I/O)
1: Enabled (this pin is forced in input pull-down mode, and
no longer used for general-purpose I/O)
Note: This bit is cleared by hardware after system reset.
Bit 12: 10
Reserved
0x0
resd
Kept at its default value.
Bit 9
SWPEN2
0x0
rw
Standby wake-up pin 2 enable
0: Disabled (this pin is used for general-purpose I/O)
1: Enabled (this pin is forced in input pull-down mode, and
no longer used for general-purpose I/O)
Note: This bit is cleared by hardware after system reset.
Bit 8
SWPEN1
0x0
rw
Standby wake-up pin 1 enable
0: Disabled (this pin is used for general-purpose I/O)
1: Enabled (this pin is forced in input pull-down mode, and
no longer used for general-purpose I/O)
Note: This bit is cleared by hardware after system reset.
Bit 7: 3
Reserved
0x00
resd
Kept at its default value.
Bit 2
PVMOF
0x0
ro
Power voltage monitoring output flag
0: Power voltage is higher than the threshold
1: Power voltage is lower than the threshold
Note: The power voltage monitor is stopped in Standby
mode.
Bit 1
SEF
0x0
ro
Standby mode entry flag
0: Device is not in Standby mode
1: Device is in Standby mode
Note: This bit is set by hardware (enter Standby mode)
and cleared by POR/LVR or by setting the CLSEF bit.
Bit 0
SWEF
0x0
ro
Standby wake-up event flag
0: No wakeup event occurred
1: A wakeup event occurred
Note:
This bit is set by hardware (on a wakeup event), and
cleared by POR/LVR or by setting the CLSWEF bit.
A wakeup event is generated by one of the following:
When the rising edge on the Standby wakeup pin occurs;
When the ERTC alarm event occurs;
If the Standby wakeup pin is enabled when the Standby
wakeup pin level is high.
3.7.3 Power control register 2 (PWC_CTRL2)
Bit
Name
Reset value
Type
Description
Bit 31: 6
Reserved
0x000000
resd
Kept at its default value.
Bit 5
VREXLPEN
0x0
rw
Voltage regulator extra low power mode enable
This bit works with the LPSEL and VRSE bits of the
PWC_CTRL register. It is applicable only when VRSEL = 1
and the device enters Deepsleep mode.
0: Voltage regulator extra low power mode disabled
1: Voltage regulator extra low power mode enabled
Note: To enable extra low-power mode, it is mandatory to
set LPSEL and VRSEL bits before setting the VREXLPEN.
Bit 4: 0
Reserved
0x0
rw
V Kept at its default value. Do not change.