ARTERY AT32F421C8T7 - Flash Address Register (FLASH_ADDR); User System Data Register (FLASH_USD); Erase;Program Protection Status Register (FLASH_EPPS)

AT32F421 Series Reference Manual
2022.11.11 Page 76 Rev 2.02
5.8.6 Flash address register (FLASH_ADDR)
Bit
Register
Reset value
Type
Description
Bit 31: 0
FA
0x0000 0000
wo
Flash address
This is used to select the address of the sectors to be
erased.
5.8.7 User system data register (FLASH_USD)
Bit
Register
Reset value
Type
Description
Bit 31: 27
Reserved
0x00
resd
Kept at its default value
Bit 26
FAP_HL
0
ro
High level Flash access protection
The status of the Flash access protection is determined
by bit 26 and bit 1.
00: Flash access protection disabled, and FAP=0xA5
01: Low-level Flash access protection enabled, and
FAP=non-oxCC and 0xA5.
10: Reserved
11: High-level Flash access protection, and FAP=0xCC
Bit 25: 18
USER_D1
0xFF
ro
User data 1
Bit 17: 10
USER_D0
0xFF
ro
User data 0
Bit 9: 2
SSB
0xFF
ro
System setting byte
Includes the system setting bytes in the loaded user
system data area
Bit 9: 7: Unused
Bit 6: nBOOT1
Bit 5: Unused
Bit 4: nSTDBY_RST
Bit 3: nDEPSLP_RST
Bit 2: nWDT_ATO_EN
Bit 1
FAP
0
ro
Flash access protection
Access to Flash memory is not allowed when this bit is
set.
Bit 0
USDERR
0
ro
User system data error
When this bit is set, it indicates that certain byte does not
match its inverse code in the user system data area. At
this point, this byte and its inverse code will be forced to
0xFF when being read.
5.8.8 Erase/program protection status register (FLASH_EPPS)
Bit
Register
Reset value
Type
Description
Bit 31: 0
EPPS
0xFFFF FFFF
ro
Erase/Program protection status
This register reflects the erase/program protection byte
status in the loaded user system data.