ARTERY AT32F421C8T7 - Table 6-2 Multiplexed Function Configuration for Port B Using GPIO_B MUX* Register; Table 6-3 Multiplexed Function Configuration for Port F Using GPIO_F MUX* Register

AT32F421 Series Reference Manual
2022.11.11 Page 86 Rev 2.02
Table 6-2 Multiplexed function configuration for port B using GPIO_B MUX* register
Pin
name
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
PB0
EVENTOUT
TMR3_C
H3
TMR1_CH
2N
USART2
_RX
I2S1_MCLK
PB1
TMR14_CH1
TMR3_C
H4
TMR1_CH
3N
SPI2_SCK/I
2S2_CK
PB2
TMR3_ET
R
PB3
SPI1_SCK/I2
S1_CK
EVENTO
UT
SPI2_SCK/I
2S2_CK
PB4
SPI1_MISO/I
2S1_MCLK
TMR3_C
H1
EVENTOU
T
TMR17
_BKIN
SPI2_MISO/I
2S2_MCLK
I2C2_SDA
PB5
SPI1_MOSI/I
2S1_SD
TMR3_C
H2
TMR16_B
KIN
I2C1_SM
BA
SPI2_MOSI/I
2S2_SD
PB6
USART1_TX
I2C1_SC
L
TMR16_C
H1N
I2S1_MCLK
PB7
USART1_RX
I2C1_SD
A
TMR17_C
H1N
PB8
I2C1_SC
L
TMR16_C
H1
PB9
IR_OUT
I2C1_SD
A
TMR17_C
H1
EVENTO
UT
I2S1_M
CLK
SPI2_CS/I2
S2_WS
PB10
I2C2_SC
L
SPI2_SCK/I
2S2_CK
PB11
EVENTOUT
I2C2_SD
A
PB12
SPI2_CS/I2S
2_WS
EVENTO
UT
TMR1_BKI
N
TMR15
_BKIN
I2C2_SMBA
PB13
SPI2_SCK/I2
S2_CK
-
TMR1_CH
1N
I2C2_S
CL
PB14
SPI2_MISO/I
2S2_MCLK
TMR15_
CH1
TMR1_CH
2N
I2C2_S
DA
PB15
SPI2_MOSI/I
2S2_SD
TMR15_
CH2
TMR1_CH
3N
TMR15_
CH1N
Table 6-3 Multiplexed function configuration for port F using GPIO_F MUX* register
Pin
name
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
PF0
I2C1_SD
A
PF1
I2C1_SC
L
PF6
I2C2_SC
L
PF7
I2C2_SD
A