ARTERY AT32F421C8T7 - Figure 14-100 Overflow Event When PRBEN=0; Figure 14-101 Overflow Event When PRBEN=1; Figure 14-102 Counter Timing Diagram with Internal Clock Divided by 4

AT32F421 Series Reference Manual
2022.11.11 Page 261 Rev 2.02
Figure 14-100 Overflow event when PRBEN=0
0 1 2 3
...
31 32 0 1 2 3
...
31 32 0 1 2 3
COUNTER
31 32 0 1
32
...
PR[15:0]
OVFIF
TMR_CLK
0DIV[15:0]
22
Clear Clear Clear
Figure 14-101 Overflow event when PRBEN=1
0 1 2 3
...
21 22 0 1 2 3
...
31 32 0 1 2 3
COUNTER
31 32 0 1
32
...
PR[15:0]
OVFIF
TMR_CLK
0DIV[15:0]
22
Clear Clear Clear
Downcounting mode
Set CMSEL[1:0]=2’b00 and OWCDIR=1’b1 in the TMRx_CTRL1 register to enable the downcounting
mode. In this mode, the counter counts from the value programmed in the TMR1_PR register down to
0, and restarts from the value programmed in the TMR1_PR register, and generates a counter underflow
event.
Figure 14-102 Counter timing diagram with internal clock divided by 4
TMR_CLK
CNT_CLK
COUNTER
OVFIF
0123
4
DIV[15：0]
32 31 30
32
PR[15：0]
Clear
Up/down counting mode
Set CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register to enable the up/down counting mode. In this mode,
the counter counts up/down alternatively. When the counter counts from the value programmed in the
TMR1_PR register down to 1, an underflow event is generated, and then restarts counting from 0; when
the counter counts from 0 to the value of the TMR1_PR register -1, an overflow event is generated, and
then restarts downcounting from the value of the TMR1_PR register. The OWCDIR bit indicates the
current counting direction.
The TWCMSEL[1:0] bit in the TMRx_CTRL1 register is also used to select the CxIF flag setting method
in up/down counting mode. In up/down counting mode 1 (TWCMSEL[1:0]=2’b01), CxIF flag can only be
set when the counter counts down; in up/down counting mode 2 (TWCMSEL[1:0]=2’b10), CxIF flag can
only be set when the counter counts up; in up/down counting mode 3 (TWCMSEL[1:0]=2’b11), CxIF flag
can be set when the counter counts up/down.
Note: The OWCDIR is ready-only in up/down counting mode.