ARTERY AT32F421C8T7 - TMR Synchronization; Figure 14-32 Example of Reset Mode; Figure 14-33 Example of Suspend Mode; Figure 14-34 Example of Trigger Mode

AT32F421 Series Reference Manual
2022.11.11 Page 190 Rev 2.02
14.2.3.5 TMR synchronization
The timers are linked together internally for timer synchronization. Master timer is selected by setting the
PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit.
Slave mode includes:
Slave mode: Reset mode
The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated
when OVFS=0.
Figure 14-32 Example of reset mode
0 1 2 3 4 5 6 7 8 9 0
1
2 3 4 5 6 7
COUNTER
30 31 32 0
...
PR[15:0]
CI1F1
TMR_CLK
0
DIV[15:0]
32
101
STIS[2：0]
OVFIF
TRGIF
100
SMSEL[2：0]
Slave mode: Suspend mode
In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the
trigger input is high and stops as soon as the trigger input is low.
Figure 14-33 Example of suspend mode
0 1 2 3 4 5 6 7 8 9
COUNTER
A B C D
10
PR[15:0]
TMR_CLK
0
DIV[15:0]
32
101
STIS[2：0]
101
SMSEL[2：0]
CI1F1
TMR_EN
CNT_CLK
Slave mode: Trigger mode
The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1)
Figure 14-34 Example of trigger mode
0 1 2 3 4 5
COUNTER
PR[15:0]
TMR_CLK
0
DIV[15:0]
32
101
STIS[2：0]
110
SMSEL[2：0]
CI1F1
TMR_EN
6 7 9 10 A B ... 30 31 0 1 2 3 48 32
OVFIF