AT32F421 Series Reference Manual
2022.11.11 Page 196 Rev 2.02
Channel 2 interrupt enable
0: Disabled
1: Enabled
Channel 1 interrupt enable
0: Disabled
1: Enabled
Overflow interrupt enable
0: Disabled
1: Enabled
14.2.4.5 Interrupt status register (TMR3_ISTS)
Kept at its default value
Channel 4 recapture flag
Please refer to C1RF description.
Channel 3 recapture flag
Please refer to C1RF description.
Channel 2 recapture flag
Please refer to C1RF description.
Channel 1 recapture flag
This bit indicates whether a recapture is detected when
C1IF=1. This bit is set by hardware, and cleared by
writing “0”.
0: No capture is detected
1: Capture is detected.
Kept at its default value
Trigger interrupt flag
This bit is set by hardware on a trigger event. It is cleared
by writing “0”.
0: No trigger event occurs
1: Trigger event is generated.
Trigger event: an active edge is detected on TRGIN
input, or any edge in suspend mode.
Kept at its default value
Channel 4 interrupt flag
Please refer to C1IF description.
Channel 3 interrupt flag
Please refer to C1IF description.
Channel 2 interrupt flag
Please refer to C1IF description.
Channel 1 interrupt flag
If the channel 1 is configured as input mode:
This bit is set by hardware on a capture event. It is
cleared by software or read access to the TMRx_C1DT
0: No capture event occurs
1: Capture event is generated
If the channel 1 is configured as output mode:
This bit is set by hardware on a compare event. It is
cleared by software.
0: No compare event occurs
1: Compare event is generated
Overflow interrupt flag
This bit is set by hardware on an overflow event. It is
cleared by software.
0: No overflow event occurs
1: Overflow event is generated. If OVFEN=0 and
OVFS=0 in the TMRx_CTRL1 register:
− An overflow event is generated when OVFG= 1 in the
TMRx_SWEVE register;
− An overflow event is generated when the counter
CVAL is reinitialized by a trigger event.
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