ARTERY AT32F421C8T7 - TMR15 Software Event Register (TMR15_SW EVT); TMR15 Channel Mode Register1 (TMR15_CM1)

AT32F421 Series Reference Manual
2022.11.11 Page 231 Rev 2.02
- Overflow event is generated when the counter value
CVAL is re-initiated by a trigger event.
14.4.4.6 TMR15 software event register (TMR15_SWEVT)
Bit
Register
Reset value
Type
Description
Bit 15: 8
Reserved
0x0
resd
Kept at its default value.
Bit 7
BRKSWTR
0x0
wo
Brake event triggered by software
This bit is set to generate a brake event by software.
0: No effect
1: Generate a brake event.
Bit 6
TRGSWTR
0x0
rw
Trigger event triggered by software
This bit is set by software to generate a trigger event.
0: No effect
1: Generate a trigger event.
Bit 5
HALLSWTR
0x0
wo
HALL event triggered by software
This bit is set by software to generate a HALL event.
0: No effect
1: Generate a HALL event.
Note: This bit is only applicable to the channels with
complementary output.
Bit 4:3
Reserved
0x0
resd
Kept at its default value.
Bit 2
C2SWTR
0x0
wo
Channel 2 event triggered by software
Please refer to C1M description
Bit 1
C1SWTR
0x0
wo
Channel 1 event triggered by software
This bit is set by software to generate a channel 1 event.
0: No effect
1: Generate a channel 1 event.
Bit 0
OVFSWTR
0x0
wo
Overflow event triggered by software
This bit is set by software to generate an overflow event.
0: No effect
1: Generate an overflow event.
14.4.4.7 TMR15 channel mode register1 (TMR15_CM1)
The channel can be used in input (capture mode) or output (compare mode). The direction of a channel
is defined by the corresponding CxC bits. All the other bits of this register have different functions in
input and output modes. The CxOx describes its function in output mode when the channel is in output
mode, while the CxIx describes its function in output mode when the channel is in input mode. Attention
must be given to the fact that the same bit can have different functions in input mode and output mode.
Output compare mode:
Bit
Register
Reset value
Type
Description
Bit 15
C2OSEN
0x0
rw
Channel 2 output switch enable
Bit 14: 12
C2OCTRL
0x0
rw
Channel 2 output control
Bit 11
C2OBEN
0x0
rw
Channel 2 output buffer enable
Bit 10
C2OIEN
0x0
rw
Channel 2 output enable immediately
Bit 9: 8
C2C
0x0
rw
Channel 2 configuration
This field is used to define the direction of the channel 2
(input or output), and the selection of input pin when
C2EN=’0’:
00: Output
01: Input, C2IN is mapped on C2IFP2
10: Input, C2IN is mapped on C1IFP2
11: Input, C2IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS
register.