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ARTERY AT32F421C8T7 - EXINT Registers; Interrupt Enable Register (EXINT_INTEN); Event Enable Register (EXINT_EVTEN); Polarity Configuration Register1 (EXINT_ POLCFG1)

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AT32F421 Series Reference Manual
2022.11.11 Page 96 Rev 2.02
Interrupt initialization procedure
Select an interrupt source by setting IOMUX_EXINTCx register (This is required if GPIO is used
as an interrupt source)
Select a trigger mode by setting EXINT_POLCFG1 and EXINT_POLCFG2 registers
Enable interrupt or event by setting EXINT_INTEN and EXINT_EVTEN registers
Generate software trigger by setting EXINT_SWTRG register (This is applied to only software
trigger interrupt)
Interrupt clear procedure
Writing “1” to the EXINT_INTSTS register to clear the interrupts generated, and the
corresponding bits in the EXINT_SWTRG register.
8.3 EXINT registers
These peripheral registers must be accessed by words (32 bits).
Table 8-1 shows EXINT register map and their reset value.
Table 8-1 External interrupt/Event controller register map and reset value
Register
Offset
Reset value
EXINT_INTEN
0x00
0x0000 0000
EXINT_EVTEN
0x04
0x0000 0000
EXINT_ POLCFG1
0x08
0x0000 0000
EXINT_ POLCFG2
0x0C
0x0000 0000
EXINT_ SWTRG
0x10
0x0000 0000
EXINT_ INTSTS
0x14
0x0000 0000
8.3.1 Interrupt enable register (EXINT_INTEN)
Bit
Register
Reset value
Type
Description
Bit 31: 22
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 21: 0
INTENx
0x00000
rw
Interrupt enable or disable on line x
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Note: Line 18 and Line 20 are reserved.
8.3.2 Event enable register (EXINT_EVTEN)
Bit
Register
Reset value
Type
Description
Bit 31: 22
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 21: 0
EVTENx
0x00000
rw
Event enable or disable on line x
0: Event request is disabled.
1: Event request is enabled.
Note: Line 18 and Line 20 are reserved.
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1)
Bit
Register
Reset value
Type
Description
Bit 31: 22
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 21: 0
RPx
0x00000
rw
Rising polarity configuration bit on line x
These bits are used to select a rising edge to trigger an
interrupt and event on line x.
0: Rising trigger on line x is disabled.
1: Rising trigger on line x is enable.
Note: Line 18 and Line 20 are reserved.

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