ARTERY AT32F421C8T7 - Clock Configuration Register (CRM_CFG)

AT32F421 Series Reference Manual
2022.11.11 Page 50 Rev 2.02
4.3.2 Clock configuration register (CRM_CFG)
Bit
Name
Reset value
Type
Description
Bit 31
Reserved
0x0
resd
Kept at its default value.
Bit 26:24
CLKOUT_SEL
0x0
rw
Clock output selection
CLKOUT_SEL[3] is the bit 16 of the CRM_MISC1
register.
0000: None
0001: Reserved
0010: LICK
0011: LEXT
0100: SCLK
0101: HICK
0110: HEXT
0111: PLL/2
1100: PLL/4
1101: USB
1110: ADC
Bit 27
Bit 23: 22
Reserved
0x00
resd
Kept at its default value.
Bit 30: 29
Bit 21: 18
PLLMULT
0x00
rw
PLL multiplication factor
000000: PLL x 2 000001: PLL x 3
000010: PLL x 4 000011: PLL x 5
……
001100: PLL x 14 001101: PLL x 15
001110: PLL x 16 001111: PLL x 16
010000: PLL x 17 010001: PLL x 18
010010: PLL x 19 010011: PLL x 20
……
111110: PLL x 63 111111: PLL x 64
Bit 17
PLLHEXTDIV
0x0
rw
HEXT division selection for PLL entry clock
0: No division
1: HEXT/2
Bit 16
PLLRCS
0x0
rw
PLL reference clock select
0: HICK-divided clock (4MHz)
1: HEXT clock
Bit 28
Bit 15: 14
ADCDIV
0x0
rw
ADC division
The PCLK divided by the following factors serves the
ADC.
000: PCLK/2
001: PCLK/4
010: PCLK/6
011: PCLK/8
100: PCLK/2
101: PCLK/12
110: PCLK/8
111: PCLK/16
Bit 13: 11
APB2DIV
0x0
rw
APB2 division
The divided HCLK is used as APB2 clock.
0xx: not divided
100: divided by 2
101: divided by 4
110: divided by 8
111: divided by 16
Note: The software must set these bits correctly to
ensure that the APB2 clock frequency does not exceed
120 MHz.
Bit 10: 8
APB1DIV
0x0
rw
APB1 division
The divided HCLK is used as APB1 clock.
0xx: not divided
100: divided by 2
101: divided by 4
110: divided by 8
111: divided by 16
Note: The software must set these bits correctly to