ARTERY AT32F421C8T7 - Additional Register (CRM_MISC1)

AT32F421 Series Reference Manual
2022.11.11 Page 58 Rev 2.02
Bit 16: 8
PLL_NS
0x01F
rw
PLL multiplication factor
PLL_NS range (31~500)
Bit 7: 4
PLL_MS
0x1
rw
PLL pre-division
PLL_MS range (1~15)
Bit 3
Reserved
0x0
resd
Kept at its default value.
Bit 2: 0
PLL_FR
0x0
rw
PLL post-division factor
PLL_FR range (0~5)
000: PLL post-division=1, divided by 1
001: PLL post-division=2, divided by 2
010: PLL post-division=4, divided by 4
011: PLL post-division=8, divided by 8
100: PLL post- division=16, divided by 16
101: PLL post- division=32, divided by 32
Others: Reserved
It should be noted the relationship between the PLL-FR
values and post-division factors.
4.3.13 Additional register (CRM_MISC1)
Bit
Name
Reset value
Type
Description
Bit 31: 28
CLKOUTDIV
0x0
rw
Clock output division
0xxx: Clock output
1000: Clock output divided by 2
1001: Clock output divided by 4
1010: Clock output divided by 8
1011: Clock output divided by 16
1100: Clock output divided by 64
1101: Clock output divided by 128
1110: Clock output divided by 256
1111: Clock output divided by 512
Bit 27: 26
Reserved
0x0
resd
Kept its default value.
Bit 25
HICKDIV
0x0
rw
HICK 6 divider selection
This bit is used to select HICK or HICK /6. If the HICK/6 is
selected, the clock frequency is 8 MHz. Otherwise, the
clock frequency is 48 MHz.
0: HICK/6
1: HICK
Note: In any case, HICK always input 4 MHz to PLL.
Bit 24: 21
Reserved
0x0
resd
Kept at its default value.
Bit 20: 17
Reserved
0x8
resd
Kept at its default value.
Bit 16
CLKOUT_SEL[3]
0x0
rw
Clock output selection
This bit works with the bit [26:24] of the CRM_CFG
register.
Bit 15: 8
Reserved
0x00
resd
Kept at its default value.
Bit 7: 0
HICKCAL_KEY
0x00
rw
HICK calibration key
The HICKCAL [7:0] can be written only when this field is
set 0x5A.