ARTERY AT32F421C8T7 - PWC Registers; Power Control Register (PWC_CTRL); Table 3-1 PW Register Map and Reset Values

AT32F421 Series Reference Manual
2022.11.11 Page 43 Rev 2.02
3.7 PWC registers
The peripheral registers must be accessed by words (32 bit)
Table 3-1 PW register map and reset values
Register abbr.
Offset
Reset value
PWC_CTRL
0x00
0x0000 0000
PWC_CTRLSTS
0x04
0x0000 0000
PWC_CTRL2
0x20
0x0000 00XX
3.7.1 Power control register (PWC_CTRL)
Bit
Name
Reset value
Type
Description
Bit 31: 9
Reserved
0x0000 00
resd
Kept at its default value.
Bit 8
BPWEN
0x0
rw
Battery powered domain write enable
0: Disabled
1: Enabled
Note:
After reset, BPR is write protected. To write, this bit must
be set.
Bit 7: 5
PVMSEL
0x0
rw
Power voltage monitoring boundary select
000: Unused, not configurable
001: 2.3 V
010: 2.4 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
Bit 4
PVMEN
0x0
rw
Power voltage monitoring enable
0: Disabled
1: Enabled
Bit 3
CLSEF
0x0
wo
Clear SEF flag
0: No effect
1: Clear the SEF flag
Note: This bit is cleared by hardware after clearing the
SEF flag. Reading this bit at any time will return all zero.
Bit 2
CLSWEF
0x0
wo
Clear SWEF flag
0: No effect
1: Clear the SWEF flag
Note:
Clear the SWEF flag after two system clock cycles.
This bit is cleared by hardware after clearing the SWEF
flag. Reading this bit at any time will return all zero.
Bit 1
LPSEL
0x0
rw
Low power mode select when Cortex™-M4F deepsleeps
0: Enter DEEPSLEEP mode
1: Enter Standby mode
Bit 0
VRSEL
0x0
rw
Voltage regulator status select in Deepsleep mode
0: Enabled
1: Low-power consumption mode