ARTERY AT32F421C8T7 - TMR16 and TMR17 Counter Value (Tmrx_Cval); TMR16 and TMR17 Division Value (Tmrx_Div); TMR16 and TMR17 Period Register (Tmrx_Pr); TMR16 and TMR17 Repetition Period Register (Tmrx_Rpr)

AT32F421 Series Reference Manual
2022.11.11 Page 253 Rev 2.02
0
0
X
0
0
Output disabled (corresponding IO disconnected from
timer, and IO floating)
Asynchronously: CxOUT=CxP, Cx_EN=0,
CxCOUT=CxCP, CxCEN=0;
If the clock is present: after a dead-time,
CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that
CxIOS and CxCIOS do not correspond to CxOUT and
CxCOUT active level.
0
0
1
0
1
0
0
1
1
1
0
0
CxEN=CxCEN=0: output disabled (corresponding IO
disconnected from timer, and IO floating)
In other cases, Off-state (corresponding channel
output inactive level)
Asynchronously: CxOUT =CxP, Cx_EN=1,
CxCOUT=CxCP, CxCEN=1;
If the clock is present: after a dead-time,
CxOUT=CxIOS, CxCOUT=CxCIOS, assuming that
CxIOS and CxCIOS do not correspond to CxOUT and
CxCOUT active level.
1
0
1
1
1
0
1
1
1
Note: If the two outputs of a channel are not used (CxEN = CxCEN = 0), CxIOS, CxCIOS, CxP and
CxCP must be cleared.
Note: The state of the external I/O pins connected to the complementary CxOUT and CxCOUT channels
depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers.
14.5.4.8 TMR16 and TMR17 counter value (TMRx_CVAL)
Bit
Register
Reset value
Type
Description
Bit 15: 0
CVAL
0x0
rw
Counter value
14.5.4.9 TMR16 and TMR17 division value (TMRx_DIV)
Bit
Register
Reset value
Type
Description
Bit 15: 0
DIV
0x0
rw
Divider value
The counter clock frequency f
CK_CNT
= f
TMR_CLK
/ (DIV[15:
0]+1).
The value of this register is transferred to the actual
prescaler register when an overflow event occurs.
14.5.4.10 TMR16 and TMR17 period register (TMRx_PR)
Bit
Register
Reset value
Type
Description
Bit 15: 0
PR
0x0
rw
Period value
This defines the period value of the TMRx counter. The
timer stops working when the period value is 0.
14.5.4.11 TMR16 and TMR17 repetition period register (TMRx_RPR)
Bit
Register
Reset value
Type
Description
Bit 15: 8
Reserved
0x0
rw
Kept at its default value.
Bit 7: 0
RPR
0x0
rw
Repetition of period value
This field is used to reduce the generation rate of overflow
events. An overflow event is generated when the
repetition counter reaches 0.
14.5.4.12 TMR16 and TMR17 channel 1 data register (TMRx_C1DT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
C1DT
0x0000
rw
Channel 1 data register
When the channel 1 is configured as input mode:
The C1DT is the CVAL value stored by the last channel
1 input event (C1IN)
When the channel 1 is configured as output mode:
C1DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C1OBEN bit, and the corresponding
output is generated on C1OUT as configured.