ARTERY AT32F421C8T7 - Channel Mode Register2 (TMR3_CM2)

AT32F421 Series Reference Manual
2022.11.11 Page 199 Rev 2.02
0111: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/4, N=8
1111: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/32, N=8
Bit 3: 2
C1IDIV
0x0
rw
Channel 1 input divider
This field defines Channel 1 input divider.
00: No divider. An input capture is generated at each
active edge.
01: An input compare is generated every 2 active edges
10: An input compare is generated every 4 active edges
11: An input compare is generated every 8 active edges
Note: the divider is reset once C1EN=’0’
Bit 1: 0
C1C
0x0
rw
Channel 1 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C1EN=’0’:
00: Output
01: Input, C1IN is mapped on C1IFP1
10: Input, C1IN is mapped on C2IFP1
11: Input, C1IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
14.2.4.8 Channel mode register2 (TMR3_CM2)
Output compare mode:
Bit
Register
Reset value
Type
Description
Bit 15
C4OSEN
0x0
rw
Channel 4 output switch enable
Bit 14: 12
C4OCTRL
0x0
rw
Channel 4 output control
Bit 11
C4OBEN
0x0
rw
Channel 4 output buffer enable
Bit 10
C4OIEN
0x0
rw
Channel 4 output enable immediately
Bit 9: 8
C4C
0x0
rw
Channel 4 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C4EN=’0’:
00: Output
01: Input, C4IN is mapped on C4IFP4
10: Input, C4IN is mapped on C3IFP4
11: Input, C4IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Bit 7
C3OSEN
0x0
rw
Channel 3 output switch enable
Bit 6: 4
C3OCTRL
0x0
rw
Channel 3 output control
Bit 3
C3OBEN
0x0
rw
Channel 3 output buffer enable
Bit 2
C3OIEN
0x0
rw
Channel 3 output enable immediately
Bit 1: 0
C3C
0x0
rw
Channel 3 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C3EN=’0’:
00: Output
01: Input, C3IN is mapped on C3IFP3
10: Input, C3IN is mapped on C4IFP3
11: Input, C3IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Input capture mode:
Bit
Register
Reset value
Type
Description
Bit 15: 12
C4DF
0x0
rw
Channel 4 digital filter
Bit 11: 10
C4IDIV
0x0
rw
Channel 4 input divider
Bit 9: 8
C4C
0x0
rw
Channel 4 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C4EN=’0’:
00: Output
01: Input, C4IN is mapped on C4IFP4
10: Input, C4IN is mapped on C3IFP4
11: Input, C4IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Bit 7: 4
C3DF
0x0
rw
Channel 3 digital filter