ARTERY AT32F421C8T7 - Control Register2 (TMR15_CTRL2); TMR15 Slave Timer Control Register (TMR15_STCTRL)

AT32F421 Series Reference Manual
2022.11.11 Page 228 Rev 2.02
14.4.4.2 Control register2 (TMR15_CTRL2)
Bit
Register
Reset value
Type
Description
Bit 31: 11
Reserved
0x0
resd
Kept at its default value.
Bit 10
C2IOS
0x0
rw
Channel 2 idle output state
Bit 9
C1CIOS
0x0
rw
Channel 1 complementary idle output state
Output OFF (OEN = 0), after dead-timer generation:
0: C1COUT=0
1: C1COUT=1
Bit 8
C1IOS
0x0
rw
Channel 1 idle output state
Output OFF (OEN = 0), after dead-timer generation
0: C1OUT=0
1: C1OUT=1
Bit 7
Reserved
0x0
resd
Kept at its default value.
Bit 6:4
PTOS
0x0
rw
Primary TMR output selection
This field is used to select the signal that TMR15 outputs
to the slave timer.
000: Reset
001: Enable
010: Overflow
011: Compare pulse
100: C1ORAW signal
101: C2ORAW signal
Bit 3
DRS
0x0
rw
DMA request source
0: Channel event
1: Overflow event
Bit 2
CCFS
0x0
rw
Channel control bit refresh select
For channels with complementary output, when the
channel control bit has buffer feature:
0: Refresh channel control bit by setting the HALL bit
1: Refresh channel control bit by setting the HALL or with
the rising edge of TRGIN.
Bit 1
Reserved
0x0
resd
Kept at its default value.
Bit 0
CBCTRL
0x0
rw
Channel buffer control
For channels with complementary output:
0: CxEN, CxCEN and CxOCTRL have no buffer feature
1: CxEN, CxCEN and CxOCTRL has buffer feature.
14.4.4.3 TMR15 slave timer control register (TMR15_STCTRL)
Bit
Register
Reset value
Type
Description
Bit 31: 8
Reserved
0x0
resd
Kept at its default value
Bit 7
STIS
0x0
rw
Subordinate TMR input selection
This field is used to select the subordinate TMR input.
000: Internal selection 0 (IS0)
001: Internal selection 1 (IS1)
010: Internal selection 2 (IS2)
011: Internal selection 3 (IS3)
100: C1IRAW input detector (C1INC)
101: Filtered input 1 (C1IF1)
110: Filtered input 2 (C1IF2)
111: Reserved
Please refer to Table 14-9 for more information on ISx for
each timer.