AT32F421 Series Reference Manual
2022.11.11 Page 236 Rev 2.02
14.4.4.9 TMR15 Counter value (TMR15_CVAL)
14.4.4.10 TMR15 Division value (TMR15_DIV)
Divider value
The counter clock frequency f
CK_CNT
= f
TMR_CLK
/(DIV[15:
0]+1).
The value of this register is moved to the actual
prescaler register when an overflow event occurs.
14.4.4.11 TMR15 period register (TMR15_PR)
Period value
This defines the period value of the TMRx counter. The
timer stops working when the period value is 0.
14.4.4.12 TMR15 repetition period register (TMR15_RPR)
Kept at its default value.
Repetition of period value
This field is used to reduce the generation rate of
overflow events. An overflow event is generated when
the repetition counter reaches 0.
14.4.4.13 TMR15 channel 1 data register (TMR15_C1DT)
Channel 1 data register
When the channel 1 is configured as input mode:
The C1DT is the CVAL value stored by the last channel
1 input event (C1IN)
When the channel 1 is configured as output mode:
C1DT is the value to be compared with the CVAL
value. Whether the written value takes effective
immediately depends on the C1OBEN bit, and the
corresponding output is generated on C1OUT as
configured.
14.4.4.14 TMR15 channel 2 data register (TMR15_C2DT)
Channel 2 data register
When the channel 2 is configured as input mode:
The C2DT is the CVAL value stored by the last channel
2 input event (C1IN)
When the channel 2 is configured as output mode:
C2DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C2OBEN bit, and the corresponding
output is generated on C2OUT as configured.
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