AT32F421 Series Reference Manual
2022.11.11 Page 201 Rev 2.02
14.2.4.11 Division value (TMR3_DIV)
Divider value
The counter clock frequency f
CK_CNT
= f
TMR_CLK
/(DIV[15:
0]+1).
DIV contains the value written at an overflow event.
14.2.4.12 Period register (TMR3_PR)
Kept at its default value.
Period value
This defines the period value of the TMRx counter. The
timer stops working when the period value is 0.
14.2.4.13 Channel 1 data register (TMR3_C1DT)
Kept at its default value.
Channel 1 data register
When the channel 1 is configured as input mode:
The C1DT is the CVAL value stored by the last channel
1 input event (C1IN)
When the channel 1 is configured as output mode:
C1DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C1OBEN bit, and the corresponding
output is generated on C1OUT as configured.
14.2.4.14 Channel 2 data register (TMR3_C2DT)
Kept at its default value.
Channel 2 data register
When the channel 2 is configured as input mode:
The C2DT is the CVAL value stored by the last channel
2 input event (C1IN)
When the channel 2 is configured as output mode:
C2DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C2OBEN bit, and the corresponding
output is generated on C2OUT as configured.
14.2.4.15 Channel 3 data register (TMR3_C3DT)
Kept at its default value.
Channel 3 data register
When the channel 3 is configured as input mode:
The C3DT is the CVAL value stored by the last channel
3 input event (C1IN)
When the channel 3 is configured as output mode:
C3DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C3OBEN bit, and the corresponding
output is generated on C3OUT as configured.
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