ARTERY AT32F421C8T7 - TMR1 Channel Mode Register2 (TMR1_CM2)

AT32F421 Series Reference Manual
2022.11.11 Page 281 Rev 2.02
0000: No filter, sampling is done at f
𝐷𝑇𝑆
1000: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/8, N=6
0001: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐶𝐾_𝐼𝑁𝑇
, N=2
1001: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/8, N=8
0010: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐶𝐾_𝐼𝑁𝑇
, N=4
1010: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/16, N=5
0011: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐶𝐾_𝐼𝑁𝑇
, N=8
1011: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/16, N=6
0100: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/2, N=6
1100: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/16, N=8
0101: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/2, N=8
1101: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/32, N=5
0110: f
𝑆𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/4, N=6
1110: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/32, N=6
0111: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/4, N=8
1111: f
𝑆𝐴𝑀𝑃𝐿𝐼𝑁𝐺
=f
𝐷𝑇𝑆
/32, N=8
Bit 3: 2
C1IDIV
0x0
rw
Channel 1 input divider
This field defines Channel 1 input divider.
00: No divider. An input capture is generated at each
active edge.
01: An input compare is generated every 2 active edges
10: An input compare is generated every 4 active edges
11: An input compare is generated every 8 active edges
Note: the divider is reset once C1EN=’0’
Bit 1: 0
C1C
0x0
rw
Channel 1 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C1EN=’0’:
00: Output
01: Input, C1IN is mapped on C1IFP1
10: Input, C1IN is mapped on C2IFP1
11: Input, C1IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
14.6.4.8 TMR1 channel mode register2 (TMR1_CM2)
The channel can be used in input (capture mode) or output (compare mode). The direction of a channel
is defined by the corresponding CxC bits. All the other bits of this register have different functions in input
and output modes. The CxOx describes its function in output mode when the channel is in output mode,
while the CxIx describes its function in output mode when the channel is in input mode. Attention must
be given to the fact that the same bit can have different functions in input mode and output mode.
Output compare mode:
Bit
Register
Reset value
Type
Description
Bit 15
C4OSEN
0x0
rw
Channel 4 output switch enable
Bit 14: 12
C4OCTRL
0x0
rw
Channel 4 output control
Bit 11
C4OBEN
0x0
rw
Channel 4 output buffer enable
Bit 10
C4OIEN
0x0
rw
Channel 4 output enable immediately
Bit 9: 8
C4C
0x0
rw
Channel 4 configuration
This field is used to define the direction of the channel 1
(input or output), and the selection of input pin when
C4EN=’0’:
00: Output
01: Input, C4IN is mapped on C4IFP4
10: Input, C4IN is mapped on C3IFP4
11: Input, C4IN is mapped on STCI. This mode works
only when the internal trigger input is selected by STIS.
Bit 7
C3OSEN
0x0
rw
Channel 3 output switch enable
Bit 6: 4
C3OCTRL
0x0
rw
Channel 3 output control
Bit 3
C3OBEN
0x0
rw
Channel 3 output buffer enable
Bit 2
C3OIEN
0x0
rw
Channel 3 output enable immediately
Bit 1: 0
C3C
0x0
rw
Channel 3 configuration