ARTERY AT32F421C8T7 - TMR Synchronization; Figure 14-119 TMR Output Control; Figure 14-120 Example of TMR Brake Function

AT32F421 Series Reference Manual
2022.11.11 Page 271 Rev 2.02
 If the brake interrupt or DMA request is enabled, the brake statue flag is set, and a brake
interrupt or DMA request can be generated.
 If AOEN=1, the OEN bit is automatically set again at the next overflow event.
Note: When the brake input is active, the OEN cannot be set, nor the status flag, BRKIF can be
cleared.
Figure 14-119 TMR output control
CxOUT(to GPIO)
holistic-out
enable state
CxEN
run state
frozen state
disable CxOUT
FCSOEN
0
1
1
0
holistic-out
disable state
active state
inactive state
state select
1
0
XOR
XOR
AND
CxIOS
CxP
CxCOUT(to GPIO)
1
0
holistic-out
enable state
CxCEN
frozen state
run state
1
0
holistic-out
disable state
state select
0
1
active state
CxCP
inactive state
CxCIOS
disable CxCOUT
FCSOEN
0
1
BRK
Clock failure event
From clock control CSS(Clock Security System)
OR
BRKV
polarity selection
BRKEN
break
trigger
break enable
OEN
break
event
AND
overflow event
AOEN
auto enable
CxCP
polarity select
CxP
polarity select
DTC(dead time)
CxORAW
OR BRKEN
break
trigger
break enable
OEN
break
event
AND
overflow event
AOEN
auto enable
BRK
TMRx_BRK
BRKV
polarity selection
Clock failure event
From clock control CSS(Clock Security System)
1
0
GPIO output enable
TMRx_BRK
1
0
OR
AND
0
1
AND
OR
FCSODIS
CxCEN
CxEN
OR
AND
FCSOEN
FCSOEN
CxCE
GPIO output enable
TMR_CHx
TMR_CHxC
Figure 14-120 Example of TMR brake function
CxORAW
Delay
Delay Delay
CxEN
CxCEN
CxIOS
CxCIOS
CxCOUT
CxOUT
BRK
AOEN
14.6.3.6 TMR synchronization
The timers are linked together internally for timer synchronization. Master timer is selected by setting the
PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit.
Slave modes include:
Slave mode: Reset mode
The counter and its prescaler can be reset by a selected trigger signal. An overflow event