AT32F421 Series Reference Manual
2022.11.11 Page 145 Rev 2.02
This bit is set by hardware when parity error occurs. It is
cleared by software. USART_STS register followed by a
USART_DT read operation)
0: No parity error occurs.
1: Parity error occurs.
12.12.2 Data register (USART_DT)
Data value
This register provides read and write function. When
transmitting with the parity bit enabled, the value written
in the MSB bit will be replaced by the parity bit. When
receiving with the parity bit enabled, the value in the MSB
bit is the received parity bit.
12.12.3 Baud rate register (USART_BAUDR)
Note: If the TEN and REN bits are both disabled, the baud counter stops counting.
Divider
This field define the USART divider.
12.12.4 Control register1 (USART_CTRL1)
USART enable
0: USART is disabled.
1: USART is enable.
Data bit num
This bit is used to program the number of data bits.
0: 8 data bits
1: 9 data bits
Wakeup mode
This bit determines the way to wake up silent mode.
0: Waken up by idle line
1: Waken up by ID match
Parity enable
This bit is used to enable hardware parity control
(generation of parity bit for transmission; detection of
parity bit for reception). When this bit is enabled, the MSB
bit of the transmitted data is replaced with the parity bit;
Check whether the parity bit of the received data is
correct.
0: Parity control is disabled.
1: Parity control is enabled.
Parity selection
This bit selects the odd or even parity after the parity
control is enabled.
0: Even parity
1: Odd parity
PERR interrupt enable
0: Interrupt is disabled.
1: Interrupt is enabled.
TDBE interrupt enable
0: Interrupt is disabled.
To Next Page