ARTERY AT32F421C8T7 - TMR1 Channel 3 Data Register (TMR1_C3 DT); TMR1 Channel 4 Data Register (TMR1_C4 DT); TMR1 Brake Register (TMR1_BRK)

AT32F421 Series Reference Manual
2022.11.11 Page 285 Rev 2.02
14.6.4.16 TMR1 channel 3 data register (TMR1_C3DT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
C3DT
0x0000
rw
Channel 3 data register
When the channel 3 is configured as input mode:
The C3DT is the CVAL value stored by the last channel
3 input event (C1IN)
When the channel 3 is configured as output mode:
C3DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C3OBEN bit, and the corresponding
output is generated on C3OUT as configured.
14.6.4.17 TMR1 channel 4 data register (TMR1_C4DT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
C4DT
0x0000
rw
Channel 4 data register
When the channel 4 is configured as input mode:
The C4DT is the CVAL value stored by the last channel
4 input event (C1IN)
When the channel 3 is configured as output mode:
C4DT is the value to be compared with the CVAL value.
Whether the written value takes effective immediately
depends on the C4OBEN bit, and the corresponding
output is generated on C4OUT as configured.
14.6.4.18 TMR1 brake register (TMR1_BRK)
Bit
Register
Reset value
Type
Description
Bit 15
OEN
0x0
rw
Output enable
This bit acts on the channels as output. It is used to
enable CxOUT and CxCOUT outputs.
0: Disabled
1: Enabled
Bit 14
AOEN
0x0
rw
Automatic output enable
OEN is set automatically at an overflow event.
0: Disabled
1: Enabled
Bit 13
BRKV
0x0
rw
Brake input validity
This bit is used to select the active level of a brake input.
0: Brake input is active low.
1 Brake input is active high.
Bit 12
BRKEN
0x0
rw
Brake enable
This bit is used to enable brake input.
0: Brake input is disabled.
1: Brake input is enabled.
Bit 11
FCSOEN
0x0
rw
Frozen channel status when holistic output enable
This bit acts on the channels that have complementary
output. It is used to set the channel state when the timer
is inactive and MOEN=1.
0: CxOUT/CxCOUT outputs are disabled.
1: CxOUT/CxCOUT outputs are enabled. Output inactive
level.
Bit 10
FCSODIS
0x0
rw
Frozen channel status when holistic output disable
This bit acts on the channels that have complementary
output. It is used to set the channel state when the timer
is inactive and MOEN=0.
0: CxOUT/CxCOUT outputs are disabled.
1: CxOUT/CxCOUT outputs are enabled. Output idle
level.
Bit 9: 8
WPC
0x0
rw
Write protection configuration
This field is used to enable write protection.
00: Write protection is OFF.
01: Write protection level 3, and the following bits are
write protected: