ARTERY AT32F421C8T7 - Polarity Configuration Register2 (EXINT_ POLCFG2); Software Trigger Register (EXINT_ SWTRG); Interrupt Status Register (EXINT_ INTSTS)

AT32F421 Series Reference Manual
2022.11.11 Page 97 Rev 2.02
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2)
Bit
Register
Reset value
Type
Description
Bit 31: 22
Reserved
0x000
resd
Forced to be 0 by hardware.
Bit 21: 0
FPx
0x00000
rw
Falling polarity configuration bit on line x
These bits are used to select a falling edge to trigger an
interrupt and event on line x.
0: Falling trigger on line x is disabled.
1: Falling trigger on line x is enabled.
Note: Line 18 and Line 20 are reserved.
8.3.5 Software trigger register (EXINT_ SWTRG)
Bit
Register
Reset value
Type
Description
Bit 31: 23
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 22: 0
SWTx
0x00000
rw
Software trigger on line x
When the corresponding bit in EXINT_INTEN register is
1, if the software writes to this bit, the hardware sets the
corresponding bit in the EXINT_INTSTS automatically to
generate an interrupt.
When the corresponding bit in the EXINT_EVTEN
register is 1, if the software writes to this bit, the hardware
generates an event on the corresponding interrupt line
automatically.
0: Default value
1: Software trigger generated
Note: This bit is cleared by writing 1 to the corresponding
bit in the EXINT_INTSTS register.
Note: Line 18 and Line 20 are reserved.
8.3.6 Interrupt status register (EXINT_ INTSTS)
Bit
Register
Reset value
Type
Description
Bit 31: 22
Reserved
0x000
resd
Forced to 0 by hardware.
Bit 21: 0
LINEx
0x00000
rw
Line x status bit
0: No interrupt occurred.
1: Interrupt occurred.
Note: This bit can be cleared by writing “1” to itself.
Note: Line 18 and Line 20 are reserved.