ARTERY AT32F421C8T7 - APB1 Peripheral Reset Register1 (CRM_APB1 RST); AHB Peripheral Clock Enable Register (CRM_AHBEN)

AT32F421 Series Reference Manual
2022.11.11 Page 53 Rev 2.02
1: Reset SCFG and CMP
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST)
Access: 0 wait state, accessible by words, half-words and bytes.
Bit
Name
Reset value
Type
Description
Bit 31: 29
Reserved
0x0
resd
Kept at its default value.
Bit 28
PWCRST
0x0
rw
PWC reset
0: Does not reset PWC
1: Reset PWC
Bit 27: 23
Reserved
0x00
resd
Kept at its default value.
Bit 22
I2C2RST
0x0
rw
I2C2 reset
0: Does not reset I2C2
1: Reset I2C2
Bit 21
I2C1RST
0x0
rw
I2C1 reset
0: Does not reset I2C1
1: Reset I2C1
Bit 20: 18
Reserved
0x0
resd
Kept at its default value.
Bit 17
USART2RST
0x0
rw
USART2 reset
0: Does not reset USART2
1: Reset USART2
Bit 16: 15
Reserved
0x0
resd
Kept at its default value.
Bit 14
SPI2RST
0x0
rw
SPI2 reset
0: Does not reset SPI2
1: Reset SPI2
Bit 13:12
Reserved
0x0
resd
Kept at its default value.
Bit 11
WWDTRST
0x0
rw
WWDT reset
0: Does not reset WWDT
1: Reset WWDT
Bit 10: 9
Reserved
0x0
resd
Kept at its default value.
Bit 8
TMR14RST
0x0
rw
TMR14 reset
0: Does not reset TMR14
1: Reset TMR14
Bit 7: 5
Reserved
0x0
resd
Kept at its default value.
Bit 4
TMR6RST
0x0
rw
TMR6 reset
0: Does not reset TMR6
1: Reset TMR6
Bit 3: 2
Reserved
0x0
resd
Kept at its default value.
Bit 1
TMR3RST
0x0
rw
TMR3 reset
0: Does not reset TMR3
1: Reset TMR3
Bit 0
Reserved
0x0
resd
Kept at its default value.
4.3.6 AHB peripheral clock enable register (CRM_AHBEN)
Access: by words, half-words and bytes.
Bit
Name
Reset value
Type
Description
Bit 31: 23
Reserved
0x000
resd
Kept at its default value.
Bit 22
GPIOFEN
0x0
rw
GPIOF clock enable
0: Disabled
1: Enabled
Bit 21: 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
GPIOCEN
0x0
rw
GPIOC clock enable
0: Disabled
1: Enabled
Bit 18
GPIOBEN
0x0
rw
GPIOB clock enable
0: Disabled
1: Enabled
Bit 17
GPIOAEN
0x0
rw
GPIOA clock enable
0: Disabled
1: Enabled
Bit 16:7
Reserved
0x000
resd
Kept at its default value.
Bit 6
CRCEN
0x0
rw
CRC clock enable