ARTERY AT32F421C8T7 - TMR16 and TMR17 Software Event Register (Tmrx_Swevt); TMR16 and TMR17 Channel Mode Register1 (Tmrx_Cm1)

AT32F421 Series Reference Manual
2022.11.11 Page 249 Rev 2.02
HALL even: CxEN, CxCEN and CxOCTRL are updated.
Bit 4: 2
Reserved
0x0
resd
Kept at its default value.
Bit 1
C1IF
0x0
rw0c
Channel 1 interrupt flag
If the channel 1 is configured as input mode:
This bit is set by hardware on a capture event. It is
cleared by software or read access to the TMRx_C1DT
0: No capture event occurs
1: Capture event is generated
If the channel 1 is configured as output mode:
This bit is set by hardware on a compare event. It is
cleared by software.
0: No compare event occurs
1: Compare event is generated
Bit 0
OVFIF
0x0
rw0c
Overflow interrupt flag
This bit is set by hardware on an overflow event. It is
cleared by software.
0: No overflow event occurs
1: Overflow event is generated. If OVFEN=0 and
OVFS=0 in the TMRx_CTRL1 register:
− An overflow event is generated when OVFG= 1 in
the TMRx_SWEVE register;
− An overflow event is generated when the counter
CVAL is reinitialized by a trigger event.
14.5.4.5 TMR16 and TMR17 software event register (TMRx_SWEVT)
Bit
Register
Reset value
Type
Description
Bit 15: 8
Reserved
0x0
resd
Kept at its default value.
Bit 7
BRKSWTR
0x0
wo
Brake event triggered by software
This bit is set by software to generate a brake event.
0: No effect
1: Generate a brake event.
Bit 6
Reserved
0x0
resd
Kept at its default value.
Bit 5
HALLSWTR
0x0
wo
HALL event triggered by software
This bit is set by software to generate a HALL event.
0: No effect
1: Generate a HALL event.
Note: This bit acts only on channels that have
complementary output.
Bit 4: 2
Reserved
0x0
resd
Kept at its default value.
Bit 1
C1SWTR
0x0
wo
Channel 1 event triggered by software
This bit is set by software to generate a channel 1 event.
0: No effect
1: Generate a channel 1 event.
Bit 0
OVFSWTR
0x0
wo
Overflow event triggered by software
This bit is set by software to generate an overflow event.
0: No effect
1: Generate an overflow event.
14.5.4.6 TMR16 and TMR17 channel mode register1 (TMRx_CM1)
The channel can be used in input (capture mode) or output (compare mode). The direction of a channel
is defined by the corresponding CxC bits. All the other bits of this register have different functions in input
and output modes. The CxOx describes its function in output mode when the channel is in output mode,
while the CxIx describes its function in output mode when the channel is in input mode. Attention must
be given to the fact that the same bit can have different functions in input mode and output mode.
Output compare mode:
Bit
Register
Reset value
Type
Description
Bit 15: 8
Reserved
0x0
resd
Kept at its default value.
Bit 7
C1OSEN
0x0
rw
Channel 1 output switch enable
0: C1ORAW is not affected by EXT input.
1: Once a high level is detect on EXT input, clear
C1ORAW.
Bit 6: 4
C1OCTRL
0x0
rw
Channel 1 output control