ARTERY AT32F421C8T7 - Figure 14-85 C1 ORAW Toggles When Counter Value Matches the C1 DT Value; Figure 14-86 Upcounting Mode and PWM Mode a; Figure 14-87 One-Pulse Mode

AT32F421 Series Reference Manual
2022.11.11 Page 244 Rev 2.02
Figure 14-85 C1ORAW toggles when counter value matches the C1DT value
0 1 2 3
...
31 32 0 1 2 3
...
31 32 0 1 2 3
COUNTER
31 32 0 1
...
PR[15:0]
C1ORAW
TMR_CLK
0DIV[15:0]
32
011
C1OCTRL
[2：0]
3
C1DT[15：0]
Figure 14-86 Upcounting mode and PWM mode A
0 1 2 3
...
31 32 0 1 2 3
...
31 32 0 1 2 3
COUNTER
31 32 0 1
...
PR[15:0]
C1ORAW
TMR_CLK
0
DIV[15:0]
32
110
C1OCTRL[2：0]
3
C1DT[15：0]
C1ORAW
0
0
CIDT[15：0]
C1ORAW
32
C1DT[15：0]
1
C1ORAW
>32
C1DT[15：0]
Figure 14-87 One-pulse mode
0
1
2
3 4 5 6
...
40 41 42 43 44
...
5F 60 61 0COUNTER
61
PR[15：0]
42
C1DT[15：0]
TRGIN
C1ORAW
C1OUT
Dead-time insertion
The channel 1 of the TMR16 and TMR17 contains a set of reverse channel output. This function is
enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to Table 14-13 for more information
about the output state of CxOUT and CxCOUT.
The dead-time is activated when switching to IDLEF state (OEN falling down to 0).
Setting both CxEN and CxCEN bits, and using DTC[7:0] bit to insert dead-time of different durations.
After the dead-time insertion, the rising edge of the CxOUT is delayed compared to the rising edge of
the reference signal; the rising edge of the CxCOU is delayed compared to the falling edge of the
reference signal.
If the delay is greater than the width of the active output, and if C1OUT and C1COUT do not generate
corresponding pulses, the dead-time should be less than the width of the active output.
Figure 14-88 gives an example of dead-time insertion when CxP=0, CxCP=0, OEN=1, CxEN=1 and