ARTERY AT32F421C8T7 - Counting Mode; Figure 14-15 Counter Structure; Figure 14-16 Overflow Event When PRBEN=0

AT32F421 Series Reference Manual
2022.11.11 Page 181 Rev 2.02
14.2.3.2 Counting mode
The TMR3 timer supports several counting modes to meet different application scenarios. It has an
internal 16-bit up, down, up/down counter.
The TMRx_PR register is used to configure the counting period. The value in the TMRx_PR is
immediately moved to the shadow register by default. When the periodic buffer is enabled (PRBEN=1),
the value in the TMRx_PR register is transferred to the shadow register at an overflow event.
The TMRx_DIV register is used to configure the counting frequency. The counter counts once every
count clock period (DIV[15:0]+1). Similar to the TMRx_PR register, when the periodic buffer is enabled,
the value in the TMRx_DIV register is updated to the shadow register at an overflow event.
Reading the TMRx_CNT register returns to the current counter value, and writing to the TMRx_CNT
register updates the current counter value to the value being written.
An overflow event is generated by default. Set OVFEN=1 in the TMRx_CTRL1 to disable generation of
update events. The OVFS bit in the TMRx_CTRL1 register is used to select overflow event source. By
default, counter overflow/underflow, setting OVFSWTR bit and the reset signal generated by the slave
timer controller in reset mode trigger the generation of an overflow event. When the OVFS bit is set, only
counter overflow/underflow triggers an overflow event.
Setting the TMREN bit (TMREN=1) enables the timer to start counting. Base on synchronization logic,
however, the actual enable signal TMR_EN is set 1 clock cycle after the TMREN is set.
Figure 14-15 Counter structure
Overflow event
(CNT_overflow)
Overflow event
TMRx_PR Preload
Overflow event
PR_shadow
1
0
TMRx_DIV Preload
PRBEN
DIV_shadow
0
1
PRBEN
DIV_counter CNT_counter
TMR_CLK
DIV_overflow
Upcounting mode
Set CMSEL[1:0]=2’b00 and OWCDIR=1’b0 in the TMRx_CTRL1 register to enable upcounting mode. In
upcounting mode, the counter counts from 0 to the value programmed in the TMRx_PR register, restarts
from 0, and generates a counter overflow event, with the OVFIF bit being set to 1. If the overflow event
is disabled, the register is no longer reloaded with the preload and re-loaded value after counter overflow
occurs, otherwise, the prescaler and re-loaded value will be updated at an overflow event.
Figure 14-16 Overflow event when PRBEN=0
0 1 2 3
...
31 32 0 1 2 3
...
31 32 0 1 2 3
COUNTER
31 32 0 1
32
...
PR[15:0]
OVFIF
TMR_CLK
0DIV[15:0]
22
Clear Clear Clear