AT32F421 Series Reference Manual
2022.11.11 Page 73 Rev 2.02
5.8.1 Flash performance select register (FLASH_PSR)
Kept at its default value.
Prefetch latency disable
0: Prefetch latency of Flash is enabled, meaning that
accessing buffer requires one system clock cycle
1: Prefetch latency of Flash is disabled, meaning that
accessing buffer requires no wait state.
Note: It is recommended to set this bit to 1 and remain
unchanged.
Prefetch enable flag 2
When this bit is set, it indicates that the Flash prefetch
buffer block 2 is enabled.
Prefetch enable 2
0: Prefetch buffer block 2 is disabled
1: Prefetch buffer block 2 is enabled.
Note: It is recommended to set this bit to 1 and remain
unchanged.
Prefetch enable flag
When this bit is set, it indicates that the Flash prefetch
buffer is enabled.
Prefetch enable
0: Prefetch is disabled
1: Prefetch is enabled.
Half cycle accelerated access enable
0: Disabled
1: Enabled
Note: There are some limitations in system clock
frequency for this feature, refer to the AT32F421 data
sheet for details.
Wait cycle
The wait states for Flash access depend on the size of
the system clock, and they are in terms of system clocks.
000: Zero wait state when 0MHz<system clock≤32MHz
001: One wait state when 32MHz<system clock≤64MHz
010: Two wait states when 64MHz<system clock ≤
96MHz
011: Three wait states when 96MHz<system clock≤
120MHz
5.8.2 Flash unlock register (FLASH_UNLOCK)
Unlock key value
This is used to unlock Flash memory bank and its
extension area.
Note: All these bits are write-only, and return 0 when being read.
5.8.3 Flash user system data unlock register
(FLASH_USD_UNLOCK)
User system data Unlock key value
Note: All these bits are write-only, and return 0 when being read.
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