ARTERY AT32F421C8T7 - General-Purpose Timer (TMR16 and TMR17); TMR16 and TMR17 Introduction; TMR16 and TMR17 Main Features; TMR16 and TMR17 Functional Overview

AT32F421 Series Reference Manual
2022.11.11 Page 239 Rev 2.02
14.5 General-purpose timer (TMR16 and TMR17)
14.5.1 TMR16 and TMR17 introduction
The general-purpose timers TMR16 and TMR17 consist of a 16-bit counter supporting upcounting mode.
Each of them has a capture/compare register, and an independent channels to achieve dead-time insert,
input capture and programmable PWM output.
14.5.2 TMR16 and TMR17 main features
 Source of count clock : internal clock, external clock and internal trigger
 16-bit upcounter and 8-bit repetition counter
 1 x independent channel for input capture, output compare, PWM generation, one-pulse mode
output and dead-time insertion
 1 x independent channel for complementary output
 TMR brake feature support
 Synchronization control between timers
 Interrupt/DMA generation on the overflow event, trigger event and channel event
 Support TMR burst DMA transfer
Figure 14-75 Block diagram of general-purpose TMR16 and TMR17
BRK
Clock failure event
From clock control CSS(Clock Security System)
TMRx_BRK
TMRx_CH1
Polarity
selection
TMRx_DIV
CNT counter
CH1 edge
detector
CH1 filter
C1IRAW
C1IN DIV
C1IFP1(C1IN)
C1DT
C1C0
IN MODE
C1C=0
OUT MODE
C1DT
CNT counter
C1ORAW
Output1
control
C1COUT
C1OUT
Dead time
DTC
DIV counter
RPR counter
preload
TMRx_RPR
preload
Overflow event
TMRx_CH1
TMRx_CH1C
CK_INT(from CRM)
CompareCapture
14.5.3 TMR16 and TMR17 functional overview
14.5.3.1 Count clock
The counters of TMR16 and TMR17 can be clocked by the internal clock (CK_INT) only.
Figure 14-76 Count clock
CK_INT(form CRM)
DIV_counter
CK_CNT
CNT_counter
Internal clock (CK_INT)
By default, the CK_INT divided by a prescaler is used to drive the counter to start counting. The
configuration process is as follows:
– Set the TMRx_DIV register to set the counting frequency;
– Set the TMRx_PR register to set the counting period;
– Set the TMREN bit in the TMRx_CTRL1 register to enable the counter.