ARTERY AT32F421C8T7 - Flash Control Register (FLASH_CTRL)

AT32F421 Series Reference Manual
2022.11.11 Page 75 Rev 2.02
5.8.5 Flash control register (FLASH_CTRL)
Bit
Register
Reset value
Type
Description
Bit 31: 8
Reserved
0x0000
resd
Kept at its default value
Bit 17
LPMEN
1
r
w
Low power mode enable
0: Low power mode disabled
1: Low power mode enabled
When this bit is set, the Flash controller lets Flash
memory go to low-power mode as soon as MCU enters
Deepsleep mode.
Bit 16
FAP_HL_DIS
0x0
rw
High level Flash access protection disable
When this bit is set, the user system data area is
automatically cleared by hardware; After a reset, it is
unlocked, and low-level access protection is still
present.
.This bit is automatically cleared by hardware by writing
1 to it.
Bit 15: 13
Reserved
0x0
resd
Kept its default value
Bit 12
ODIFE
0
rw
Operation done flag interrupt enable
0: Operation complete interrupt disabled
1: Operation complete interrupt enabled
Bit 11,8,3
Reserved
0
resd
Kept its default value
Bit 10
ERRIE
0
rw
Error interrupt enable
This bit enables EPPERR or PROGERR interrupt.
0: Interrupt is disabled;
1: Interrupt is enabled.
Bit 9
USDULKS
0
rw
User system data unlock success
This bit is set by hardware when the user system data is
unlocked successfully, indicating that erase/program
operation to the user system data is allowed.
This bit is cleared by writing “0”, which will re-lock the user
system data area.
Bit 7
OPLK
1
rw
Operation lock
This bit is set by default, indicating that Flash memory is
protected against operations. This bit is cleared by
hardware after unlock, indicating that erase/program
operation to Flash memory is allowed. Writing “1” can re-
lock Flash memory operations.
Bit 6
ERSTR
0
rw
Erase start
An erase operation is triggered when this bit is set by
software. This bit is cleared by hardware after the
completion of the erase operation.
Bit 5
USDERS
0
rw
User system data erase
It indicates the user system data erase.
Bit 4
USDPRGM
0
rw
User system data program
It indicates the user system data program.
Bit 2
BANKERS
0
rw
Bank erase
It indicates bank erase operation.
Bit 1
SECERS
0
rw
Sector erase
It indicates sector erase operation.
Bit 0
FPRGM
0
rw
Flash program
It indicates Flash program operation.