ARTERY AT32F421C8T7 - IOMUX Function Input;Output; Table 6-1 Multiplexed Function Configuration for Port a Using GPIO_A MUX* Register

AT32F421 Series Reference Manual
2022.11.11 Page 85 Rev 2.02
6.2.9 IOMUX function input/output
The selection of the valid multiplexed functions for each port is done by the GPIOx_MUXL (for pin 0 to
pin 7) or GPIOx_MUXH (for pin 8 to pin 15) registers.
Table 6-1 Multiplexed function configuration for port A using GPIO_A MUX* register
Pin
name
MUX0
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
MUX7
PA0
USART2_
CTS
I2C2_SC
L
TMR1_E
TR
COMP_O
UT
PA1
EVENTOUT
USART2_
RTS
I2C2_SD
A
TMR15_
CH1N
PA2
TMR15_CH1
USART2_T
X
PA3
TMR15_CH2
USART2_
RX
I2S2_MC
LK
PA4
SPI1_CS/I2S
1_WS
USART2_
CK
TMR14_
CH1
PA5
SPI1_SCK/I2
S1_CK
PA6
SPI1_MISO/I
2S1_MCLK
TMR3_CH
1
TMR1_BKI
N
I2S2_MC
LK
TMR16_
CH1
EVENTO
UT
COMP_O
UT
PA7
SPI1_MOSI/I
2S1_SD
TMR3_CH
2
TMR1_CH
1N
TMR14_
CH1
TMR17_
CH1
EVENTO
UT
PA8
CLKOUT
USART1_
CK
TMR1_CH
1
EVENTO
UT
USART2
_TX
I2C2_SCL
PA9
TMR15_BKI
N
USART1_T
X
TMR1_CH
2
I2C1_SC
L
CLKOUT
I2C2_SM
BA
PA10
TMR17_BKI
N
USART1_
RX
TMR1_CH
3
I2C1_SD
A
PA11
EVENTOUT
USART1_
CTS
TMR1_CH
4
I2C1_SM
BA
I2C2_SC
L
COMP_O
UT
PA12
EVENTOUT
USART1_
RTS
TMR1_ET
R
I2C2_SD
A
PA13
SWDIO
IR_OUT
SPI2_MI
SO/I2S2
_MCLK
PA14
SWCLK
USART2_T
X
SPI2_M
OSI/I2S2
_SD
PA15
SPI1_CS/I2S
1_WS
USART2_
RX
EVENTO
UT
SPI2_CS
/I2S2_W
S