ARTERY AT32F421C8T7 - Page 3

AT32F421 Series Reference Manual
2022.11.11 Page 3 Rev 2.02
4.1.1 Clock sources ............................................................................. 45
4.1.2 System clock ............................................................................... 46
4.1.3 Peripheral clock .......................................................................... 46
4.1.4 Clock fail detector ....................................................................... 47
4.1.5 Auto step-by-step system clock switch .......................................... 47
4.1.6 Internal clock output .................................................................... 47
4.1.7 Interrupts .................................................................................... 47
4.2 Reset .......................................................................................... 47
4.2.1 System reset ............................................................................... 47
4.2.2 Battery powered domain reset ...................................................... 48
4.3 CRM registers ............................................................................. 48
4.3.1 Clock control register (CRM_CTRL) .............................................. 49
4.3.2 Clock configuration register (CRM_CFG) ...................................... 50
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 51
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 52
4.3.5 APB1 peripheral reset register1 (CRM_APB1RST) ........................ 53
4.3.6 AHB peripheral clock enable register (CRM_AHBEN) .................... 53
4.3.7 APB2 peripheral clock enable register (CRM_APB2EN) ................. 54
4.3.8 APB1 peripheral clock enable register (CRM_APB1EN) ................. 55
4.3.9 Battery powered domain control register (CRM_BPDC).................. 56
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 56
4.3.11 AHB peripheral reset register (CRM_AHBRST) ............................. 57
4.3.12 PLL configuration register (CRM_PLL) .......................................... 57
4.3.13 Additional register (CRM_MISC1) ................................................. 58
4.3.14 Additional register (CRM_MISC2) ................................................. 59
5 Embedded Flash memory controller (FLASH) ............................... 60
5.1 FLASH introduction ...................................................................... 60
5.2 Flash memory operation ............................................................... 62
5.2.1 Unlock/lock ................................................................................. 62
5.2.2 Erase operation ........................................................................... 62
5.2.3 Programming operation................................................................ 64
5.2.4 Read operation ........................................................................... 65
5.3 Main Flash memory extension area ............................................... 65
5.4 User system data area ................................................................. 66